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[RISCV] Don't emit vxrm writes for vnclip(u).wi with shift of 0. (#76578)
If there's no shift being performed, the rounding mode doesn't matter. We could do the same for vssra and vssrl, but they are no-ops with a shift of 0 so would be better off being removed earlier.
1 parent 9fd03cb commit bf684a9

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3 files changed

+12
-41
lines changed

3 files changed

+12
-41
lines changed

‎llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -198,13 +198,23 @@ char RISCVInsertWriteVXRM::ID = 0;
198198
INITIALIZE_PASS(RISCVInsertWriteVXRM, DEBUG_TYPE, RISCV_INSERT_WRITE_VXRM_NAME,
199199
false, false)
200200

201+
static bool ignoresVXRM(const MachineInstr &MI) {
202+
switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
203+
default:
204+
return false;
205+
case RISCV::VNCLIP_WI:
206+
case RISCV::VNCLIPU_WI:
207+
return MI.getOperand(3).getImm() == 0;
208+
}
209+
}
210+
201211
bool RISCVInsertWriteVXRM::computeVXRMChanges(const MachineBasicBlock &MBB) {
202212
BlockData &BBInfo = BlockInfo[MBB.getNumber()];
203213

204214
bool NeedVXRMWrite = false;
205215
for (const MachineInstr &MI : MBB) {
206216
int VXRMIdx = RISCVII::getVXRMOpNum(MI.getDesc());
207-
if (VXRMIdx >= 0) {
217+
if (VXRMIdx >= 0 && !ignoresVXRM(MI)) {
208218
unsigned NewVXRMImm = MI.getOperand(VXRMIdx).getImm();
209219

210220
if (!BBInfo.VXRMUse.isValid())
@@ -356,7 +366,7 @@ void RISCVInsertWriteVXRM::emitWriteVXRM(MachineBasicBlock &MBB) {
356366

357367
for (MachineInstr &MI : MBB) {
358368
int VXRMIdx = RISCVII::getVXRMOpNum(MI.getDesc());
359-
if (VXRMIdx >= 0) {
369+
if (VXRMIdx >= 0 && !ignoresVXRM(MI)) {
360370
unsigned NewVXRMImm = MI.getOperand(VXRMIdx).getImm();
361371

362372
if (PendingInsert || !Info.isStatic() ||

‎llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll

Lines changed: 0 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,6 @@ define <2 x i32> @stest_f64i32(<2 x double> %x) {
4040
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
4141
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
4242
; CHECK-V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
43-
; CHECK-V-NEXT: csrwi vxrm, 0
4443
; CHECK-V-NEXT: vnclip.wi v8, v8, 0
4544
; CHECK-V-NEXT: ret
4645
entry:
@@ -77,7 +76,6 @@ define <2 x i32> @utest_f64i32(<2 x double> %x) {
7776
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
7877
; CHECK-V-NEXT: vfcvt.rtz.xu.f.v v8, v8
7978
; CHECK-V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
80-
; CHECK-V-NEXT: csrwi vxrm, 0
8179
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
8280
; CHECK-V-NEXT: ret
8381
entry:
@@ -193,7 +191,6 @@ define <4 x i32> @stest_f32i32(<4 x float> %x) {
193191
; CHECK-V: # %bb.0: # %entry
194192
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
195193
; CHECK-V-NEXT: vfwcvt.rtz.x.f.v v10, v8
196-
; CHECK-V-NEXT: csrwi vxrm, 0
197194
; CHECK-V-NEXT: vnclip.wi v8, v10, 0
198195
; CHECK-V-NEXT: ret
199196
entry:
@@ -247,7 +244,6 @@ define <4 x i32> @utest_f32i32(<4 x float> %x) {
247244
; CHECK-V: # %bb.0: # %entry
248245
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
249246
; CHECK-V-NEXT: vfwcvt.rtz.xu.f.v v10, v8
250-
; CHECK-V-NEXT: csrwi vxrm, 0
251247
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
252248
; CHECK-V-NEXT: ret
253249
entry:
@@ -497,7 +493,6 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) {
497493
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
498494
; CHECK-V-NEXT: vslideup.vi v10, v8, 3
499495
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
500-
; CHECK-V-NEXT: csrwi vxrm, 0
501496
; CHECK-V-NEXT: vnclip.wi v8, v10, 0
502497
; CHECK-V-NEXT: csrr a0, vlenb
503498
; CHECK-V-NEXT: slli a0, a0, 2
@@ -666,7 +661,6 @@ define <4 x i32> @utesth_f16i32(<4 x half> %x) {
666661
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
667662
; CHECK-V-NEXT: vslideup.vi v10, v8, 3
668663
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
669-
; CHECK-V-NEXT: csrwi vxrm, 0
670664
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
671665
; CHECK-V-NEXT: csrr a0, vlenb
672666
; CHECK-V-NEXT: slli a0, a0, 2
@@ -907,7 +901,6 @@ define <2 x i16> @stest_f64i16(<2 x double> %x) {
907901
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
908902
; CHECK-V-NEXT: vfncvt.rtz.x.f.w v9, v8
909903
; CHECK-V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
910-
; CHECK-V-NEXT: csrwi vxrm, 0
911904
; CHECK-V-NEXT: vnclip.wi v8, v9, 0
912905
; CHECK-V-NEXT: ret
913906
entry:
@@ -944,7 +937,6 @@ define <2 x i16> @utest_f64i16(<2 x double> %x) {
944937
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
945938
; CHECK-V-NEXT: vfncvt.rtz.xu.f.w v9, v8
946939
; CHECK-V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
947-
; CHECK-V-NEXT: csrwi vxrm, 0
948940
; CHECK-V-NEXT: vnclipu.wi v8, v9, 0
949941
; CHECK-V-NEXT: ret
950942
entry:
@@ -1063,7 +1055,6 @@ define <4 x i16> @stest_f32i16(<4 x float> %x) {
10631055
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
10641056
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
10651057
; CHECK-V-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
1066-
; CHECK-V-NEXT: csrwi vxrm, 0
10671058
; CHECK-V-NEXT: vnclip.wi v8, v8, 0
10681059
; CHECK-V-NEXT: ret
10691060
entry:
@@ -1118,7 +1109,6 @@ define <4 x i16> @utest_f32i16(<4 x float> %x) {
11181109
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
11191110
; CHECK-V-NEXT: vfcvt.rtz.xu.f.v v8, v8
11201111
; CHECK-V-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
1121-
; CHECK-V-NEXT: csrwi vxrm, 0
11221112
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
11231113
; CHECK-V-NEXT: ret
11241114
entry:
@@ -1495,7 +1485,6 @@ define <8 x i16> @stest_f16i16(<8 x half> %x) {
14951485
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
14961486
; CHECK-V-NEXT: vslideup.vi v10, v8, 7
14971487
; CHECK-V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
1498-
; CHECK-V-NEXT: csrwi vxrm, 0
14991488
; CHECK-V-NEXT: vnclip.wi v8, v10, 0
15001489
; CHECK-V-NEXT: csrr a0, vlenb
15011490
; CHECK-V-NEXT: slli a0, a0, 1
@@ -1774,7 +1763,6 @@ define <8 x i16> @utesth_f16i16(<8 x half> %x) {
17741763
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
17751764
; CHECK-V-NEXT: vslideup.vi v10, v8, 7
17761765
; CHECK-V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
1777-
; CHECK-V-NEXT: csrwi vxrm, 0
17781766
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
17791767
; CHECK-V-NEXT: csrr a0, vlenb
17801768
; CHECK-V-NEXT: slli a0, a0, 1
@@ -3349,7 +3337,6 @@ define <2 x i32> @stest_f64i32_mm(<2 x double> %x) {
33493337
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
33503338
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
33513339
; CHECK-V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
3352-
; CHECK-V-NEXT: csrwi vxrm, 0
33533340
; CHECK-V-NEXT: vnclip.wi v8, v8, 0
33543341
; CHECK-V-NEXT: ret
33553342
entry:
@@ -3384,7 +3371,6 @@ define <2 x i32> @utest_f64i32_mm(<2 x double> %x) {
33843371
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
33853372
; CHECK-V-NEXT: vfcvt.rtz.xu.f.v v8, v8
33863373
; CHECK-V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
3387-
; CHECK-V-NEXT: csrwi vxrm, 0
33883374
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
33893375
; CHECK-V-NEXT: ret
33903376
entry:
@@ -3497,7 +3483,6 @@ define <4 x i32> @stest_f32i32_mm(<4 x float> %x) {
34973483
; CHECK-V: # %bb.0: # %entry
34983484
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
34993485
; CHECK-V-NEXT: vfwcvt.rtz.x.f.v v10, v8
3500-
; CHECK-V-NEXT: csrwi vxrm, 0
35013486
; CHECK-V-NEXT: vnclip.wi v8, v10, 0
35023487
; CHECK-V-NEXT: ret
35033488
entry:
@@ -3549,7 +3534,6 @@ define <4 x i32> @utest_f32i32_mm(<4 x float> %x) {
35493534
; CHECK-V: # %bb.0: # %entry
35503535
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
35513536
; CHECK-V-NEXT: vfwcvt.rtz.xu.f.v v10, v8
3552-
; CHECK-V-NEXT: csrwi vxrm, 0
35533537
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
35543538
; CHECK-V-NEXT: ret
35553539
entry:
@@ -3796,7 +3780,6 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
37963780
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
37973781
; CHECK-V-NEXT: vslideup.vi v10, v8, 3
37983782
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
3799-
; CHECK-V-NEXT: csrwi vxrm, 0
38003783
; CHECK-V-NEXT: vnclip.wi v8, v10, 0
38013784
; CHECK-V-NEXT: csrr a0, vlenb
38023785
; CHECK-V-NEXT: slli a0, a0, 2
@@ -3963,7 +3946,6 @@ define <4 x i32> @utesth_f16i32_mm(<4 x half> %x) {
39633946
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
39643947
; CHECK-V-NEXT: vslideup.vi v10, v8, 3
39653948
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
3966-
; CHECK-V-NEXT: csrwi vxrm, 0
39673949
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
39683950
; CHECK-V-NEXT: csrr a0, vlenb
39693951
; CHECK-V-NEXT: slli a0, a0, 2
@@ -4201,7 +4183,6 @@ define <2 x i16> @stest_f64i16_mm(<2 x double> %x) {
42014183
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
42024184
; CHECK-V-NEXT: vfncvt.rtz.x.f.w v9, v8
42034185
; CHECK-V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
4204-
; CHECK-V-NEXT: csrwi vxrm, 0
42054186
; CHECK-V-NEXT: vnclip.wi v8, v9, 0
42064187
; CHECK-V-NEXT: ret
42074188
entry:
@@ -4236,7 +4217,6 @@ define <2 x i16> @utest_f64i16_mm(<2 x double> %x) {
42364217
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
42374218
; CHECK-V-NEXT: vfncvt.rtz.xu.f.w v9, v8
42384219
; CHECK-V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
4239-
; CHECK-V-NEXT: csrwi vxrm, 0
42404220
; CHECK-V-NEXT: vnclipu.wi v8, v9, 0
42414221
; CHECK-V-NEXT: ret
42424222
entry:
@@ -4352,7 +4332,6 @@ define <4 x i16> @stest_f32i16_mm(<4 x float> %x) {
43524332
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
43534333
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
43544334
; CHECK-V-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
4355-
; CHECK-V-NEXT: csrwi vxrm, 0
43564335
; CHECK-V-NEXT: vnclip.wi v8, v8, 0
43574336
; CHECK-V-NEXT: ret
43584337
entry:
@@ -4405,7 +4384,6 @@ define <4 x i16> @utest_f32i16_mm(<4 x float> %x) {
44054384
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
44064385
; CHECK-V-NEXT: vfcvt.rtz.xu.f.v v8, v8
44074386
; CHECK-V-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
4408-
; CHECK-V-NEXT: csrwi vxrm, 0
44094387
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
44104388
; CHECK-V-NEXT: ret
44114389
entry:
@@ -4779,7 +4757,6 @@ define <8 x i16> @stest_f16i16_mm(<8 x half> %x) {
47794757
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
47804758
; CHECK-V-NEXT: vslideup.vi v10, v8, 7
47814759
; CHECK-V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
4782-
; CHECK-V-NEXT: csrwi vxrm, 0
47834760
; CHECK-V-NEXT: vnclip.wi v8, v10, 0
47844761
; CHECK-V-NEXT: csrr a0, vlenb
47854762
; CHECK-V-NEXT: slli a0, a0, 1
@@ -5054,7 +5031,6 @@ define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) {
50545031
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
50555032
; CHECK-V-NEXT: vslideup.vi v10, v8, 7
50565033
; CHECK-V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
5057-
; CHECK-V-NEXT: csrwi vxrm, 0
50585034
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
50595035
; CHECK-V-NEXT: csrr a0, vlenb
50605036
; CHECK-V-NEXT: slli a0, a0, 1

‎llvm/test/CodeGen/RISCV/rvv/trunc-sat-clip.ll

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,6 @@ define void @trunc_sat_i8i16_maxmin(ptr %x, ptr %y) {
2020
; CHECK: # %bb.0:
2121
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
2222
; CHECK-NEXT: vle16.v v8, (a0)
23-
; CHECK-NEXT: csrwi vxrm, 0
2423
; CHECK-NEXT: vnclip.wi v8, v8, 0
2524
; CHECK-NEXT: vse8.v v8, (a1)
2625
; CHECK-NEXT: ret
@@ -37,7 +36,6 @@ define void @trunc_sat_i8i16_minmax(ptr %x, ptr %y) {
3736
; CHECK: # %bb.0:
3837
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
3938
; CHECK-NEXT: vle16.v v8, (a0)
40-
; CHECK-NEXT: csrwi vxrm, 0
4139
; CHECK-NEXT: vnclip.wi v8, v8, 0
4240
; CHECK-NEXT: vse8.v v8, (a1)
4341
; CHECK-NEXT: ret
@@ -75,7 +73,6 @@ define void @trunc_sat_u8u16_min(ptr %x, ptr %y) {
7573
; CHECK: # %bb.0:
7674
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
7775
; CHECK-NEXT: vle16.v v8, (a0)
78-
; CHECK-NEXT: csrwi vxrm, 0
7976
; CHECK-NEXT: vnclipu.wi v8, v8, 0
8077
; CHECK-NEXT: vse8.v v8, (a1)
8178
; CHECK-NEXT: ret
@@ -109,7 +106,6 @@ define void @trunc_sat_u8u16_maxmin(ptr %x, ptr %y) {
109106
; CHECK: # %bb.0:
110107
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
111108
; CHECK-NEXT: vle16.v v8, (a0)
112-
; CHECK-NEXT: csrwi vxrm, 0
113109
; CHECK-NEXT: vnclipu.wi v8, v8, 0
114110
; CHECK-NEXT: vse8.v v8, (a1)
115111
; CHECK-NEXT: ret
@@ -126,7 +122,6 @@ define void @trunc_sat_u8u16_minmax(ptr %x, ptr %y) {
126122
; CHECK: # %bb.0:
127123
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
128124
; CHECK-NEXT: vle16.v v8, (a0)
129-
; CHECK-NEXT: csrwi vxrm, 0
130125
; CHECK-NEXT: vnclipu.wi v8, v8, 0
131126
; CHECK-NEXT: vse8.v v8, (a1)
132127
; CHECK-NEXT: ret
@@ -166,7 +161,6 @@ define void @trunc_sat_i16i32_maxmin(ptr %x, ptr %y) {
166161
; CHECK: # %bb.0:
167162
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
168163
; CHECK-NEXT: vle32.v v8, (a0)
169-
; CHECK-NEXT: csrwi vxrm, 0
170164
; CHECK-NEXT: vnclip.wi v8, v8, 0
171165
; CHECK-NEXT: vse16.v v8, (a1)
172166
; CHECK-NEXT: ret
@@ -183,7 +177,6 @@ define void @trunc_sat_i16i32_minmax(ptr %x, ptr %y) {
183177
; CHECK: # %bb.0:
184178
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
185179
; CHECK-NEXT: vle32.v v8, (a0)
186-
; CHECK-NEXT: csrwi vxrm, 0
187180
; CHECK-NEXT: vnclip.wi v8, v8, 0
188181
; CHECK-NEXT: vse16.v v8, (a1)
189182
; CHECK-NEXT: ret
@@ -219,7 +212,6 @@ define void @trunc_sat_u16u32_min(ptr %x, ptr %y) {
219212
; CHECK: # %bb.0:
220213
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
221214
; CHECK-NEXT: vle32.v v8, (a0)
222-
; CHECK-NEXT: csrwi vxrm, 0
223215
; CHECK-NEXT: vnclipu.wi v8, v8, 0
224216
; CHECK-NEXT: vse16.v v8, (a1)
225217
; CHECK-NEXT: ret
@@ -235,7 +227,6 @@ define void @trunc_sat_u16u32_minmax(ptr %x, ptr %y) {
235227
; CHECK: # %bb.0:
236228
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
237229
; CHECK-NEXT: vle32.v v8, (a0)
238-
; CHECK-NEXT: csrwi vxrm, 0
239230
; CHECK-NEXT: vnclipu.wi v8, v8, 0
240231
; CHECK-NEXT: vse16.v v8, (a1)
241232
; CHECK-NEXT: ret
@@ -252,7 +243,6 @@ define void @trunc_sat_u16u32_maxmin(ptr %x, ptr %y) {
252243
; CHECK: # %bb.0:
253244
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
254245
; CHECK-NEXT: vle32.v v8, (a0)
255-
; CHECK-NEXT: csrwi vxrm, 0
256246
; CHECK-NEXT: vnclipu.wi v8, v8, 0
257247
; CHECK-NEXT: vse16.v v8, (a1)
258248
; CHECK-NEXT: ret
@@ -293,7 +283,6 @@ define void @trunc_sat_i32i64_maxmin(ptr %x, ptr %y) {
293283
; CHECK: # %bb.0:
294284
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
295285
; CHECK-NEXT: vle64.v v8, (a0)
296-
; CHECK-NEXT: csrwi vxrm, 0
297286
; CHECK-NEXT: vnclip.wi v10, v8, 0
298287
; CHECK-NEXT: vse32.v v10, (a1)
299288
; CHECK-NEXT: ret
@@ -310,7 +299,6 @@ define void @trunc_sat_i32i64_minmax(ptr %x, ptr %y) {
310299
; CHECK: # %bb.0:
311300
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
312301
; CHECK-NEXT: vle64.v v8, (a0)
313-
; CHECK-NEXT: csrwi vxrm, 0
314302
; CHECK-NEXT: vnclip.wi v10, v8, 0
315303
; CHECK-NEXT: vse32.v v10, (a1)
316304
; CHECK-NEXT: ret
@@ -347,7 +335,6 @@ define void @trunc_sat_u32u64_min(ptr %x, ptr %y) {
347335
; CHECK: # %bb.0:
348336
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
349337
; CHECK-NEXT: vle64.v v8, (a0)
350-
; CHECK-NEXT: csrwi vxrm, 0
351338
; CHECK-NEXT: vnclipu.wi v10, v8, 0
352339
; CHECK-NEXT: vse32.v v10, (a1)
353340
; CHECK-NEXT: ret
@@ -364,7 +351,6 @@ define void @trunc_sat_u32u64_maxmin(ptr %x, ptr %y) {
364351
; CHECK: # %bb.0:
365352
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
366353
; CHECK-NEXT: vle64.v v8, (a0)
367-
; CHECK-NEXT: csrwi vxrm, 0
368354
; CHECK-NEXT: vnclipu.wi v10, v8, 0
369355
; CHECK-NEXT: vse32.v v10, (a1)
370356
; CHECK-NEXT: ret
@@ -381,7 +367,6 @@ define void @trunc_sat_u32u64_minmax(ptr %x, ptr %y) {
381367
; CHECK: # %bb.0:
382368
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
383369
; CHECK-NEXT: vle64.v v8, (a0)
384-
; CHECK-NEXT: csrwi vxrm, 0
385370
; CHECK-NEXT: vnclipu.wi v10, v8, 0
386371
; CHECK-NEXT: vse32.v v10, (a1)
387372
; CHECK-NEXT: ret

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