@@ -141,37 +141,23 @@ entry:
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}
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define i32 @add_v4i16_v4i32_zext (<4 x i16 > %x ) {
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- ; CHECK-SD-LABEL: add_v4i16_v4i32_zext:
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- ; CHECK-SD: // %bb.0: // %entry
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- ; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
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- ; CHECK-SD-NEXT: addv s0, v0.4s
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- ; CHECK-SD-NEXT: fmov w0, s0
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- ; CHECK-SD-NEXT: ret
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- ;
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- ; CHECK-GI-LABEL: add_v4i16_v4i32_zext:
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- ; CHECK-GI: // %bb.0: // %entry
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- ; CHECK-GI-NEXT: uaddlv s0, v0.4h
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- ; CHECK-GI-NEXT: fmov w0, s0
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- ; CHECK-GI-NEXT: ret
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+ ; CHECK-LABEL: add_v4i16_v4i32_zext:
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+ ; CHECK: // %bb.0: // %entry
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+ ; CHECK-NEXT: uaddlv s0, v0.4h
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+ ; CHECK-NEXT: fmov w0, s0
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+ ; CHECK-NEXT: ret
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entry:
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%xx = zext <4 x i16 > %x to <4 x i32 >
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%z = call i32 @llvm.vector.reduce.add.v4i32 (<4 x i32 > %xx )
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ret i32 %z
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}
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define i32 @add_v4i16_v4i32_sext (<4 x i16 > %x ) {
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- ; CHECK-SD-LABEL: add_v4i16_v4i32_sext:
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- ; CHECK-SD: // %bb.0: // %entry
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- ; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
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- ; CHECK-SD-NEXT: addv s0, v0.4s
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- ; CHECK-SD-NEXT: fmov w0, s0
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- ; CHECK-SD-NEXT: ret
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- ;
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- ; CHECK-GI-LABEL: add_v4i16_v4i32_sext:
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- ; CHECK-GI: // %bb.0: // %entry
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- ; CHECK-GI-NEXT: saddlv s0, v0.4h
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- ; CHECK-GI-NEXT: fmov w0, s0
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- ; CHECK-GI-NEXT: ret
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+ ; CHECK-LABEL: add_v4i16_v4i32_sext:
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+ ; CHECK: // %bb.0: // %entry
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+ ; CHECK-NEXT: saddlv s0, v0.4h
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+ ; CHECK-NEXT: fmov w0, s0
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+ ; CHECK-NEXT: ret
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entry:
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%xx = sext <4 x i16 > %x to <4 x i32 >
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%z = call i32 @llvm.vector.reduce.add.v4i32 (<4 x i32 > %xx )
@@ -483,8 +469,7 @@ define i32 @add_v4i8_v4i32_zext(<4 x i8> %x) {
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; CHECK-SD-LABEL: add_v4i8_v4i32_zext:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
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- ; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
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- ; CHECK-SD-NEXT: addv s0, v0.4s
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+ ; CHECK-SD-NEXT: uaddlv s0, v0.4h
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; CHECK-SD-NEXT: fmov w0, s0
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; CHECK-SD-NEXT: ret
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;
@@ -589,8 +574,7 @@ entry:
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define signext i16 @add_v8i8_v8i16_sext (<8 x i8 > %x ) {
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; CHECK-SD-LABEL: add_v8i8_v8i16_sext:
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; CHECK-SD: // %bb.0: // %entry
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- ; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
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- ; CHECK-SD-NEXT: addv h0, v0.8h
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+ ; CHECK-SD-NEXT: saddlv h0, v0.8b
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; CHECK-SD-NEXT: smov w0, v0.h[0]
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; CHECK-SD-NEXT: ret
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;
@@ -939,20 +923,12 @@ entry:
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}
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define i32 @add_v4i16_v4i32_acc_zext (<4 x i16 > %x , i32 %a ) {
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- ; CHECK-SD-LABEL: add_v4i16_v4i32_acc_zext:
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- ; CHECK-SD: // %bb.0: // %entry
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- ; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
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- ; CHECK-SD-NEXT: addv s0, v0.4s
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- ; CHECK-SD-NEXT: fmov w8, s0
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- ; CHECK-SD-NEXT: add w0, w8, w0
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- ; CHECK-SD-NEXT: ret
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- ;
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- ; CHECK-GI-LABEL: add_v4i16_v4i32_acc_zext:
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- ; CHECK-GI: // %bb.0: // %entry
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- ; CHECK-GI-NEXT: uaddlv s0, v0.4h
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- ; CHECK-GI-NEXT: fmov w8, s0
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- ; CHECK-GI-NEXT: add w0, w8, w0
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- ; CHECK-GI-NEXT: ret
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+ ; CHECK-LABEL: add_v4i16_v4i32_acc_zext:
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+ ; CHECK: // %bb.0: // %entry
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+ ; CHECK-NEXT: uaddlv s0, v0.4h
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+ ; CHECK-NEXT: fmov w8, s0
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+ ; CHECK-NEXT: add w0, w8, w0
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+ ; CHECK-NEXT: ret
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entry:
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%xx = zext <4 x i16 > %x to <4 x i32 >
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%z = call i32 @llvm.vector.reduce.add.v4i32 (<4 x i32 > %xx )
@@ -961,20 +937,12 @@ entry:
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}
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define i32 @add_v4i16_v4i32_acc_sext (<4 x i16 > %x , i32 %a ) {
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- ; CHECK-SD-LABEL: add_v4i16_v4i32_acc_sext:
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- ; CHECK-SD: // %bb.0: // %entry
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- ; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
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- ; CHECK-SD-NEXT: addv s0, v0.4s
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- ; CHECK-SD-NEXT: fmov w8, s0
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- ; CHECK-SD-NEXT: add w0, w8, w0
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- ; CHECK-SD-NEXT: ret
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- ;
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- ; CHECK-GI-LABEL: add_v4i16_v4i32_acc_sext:
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- ; CHECK-GI: // %bb.0: // %entry
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- ; CHECK-GI-NEXT: saddlv s0, v0.4h
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- ; CHECK-GI-NEXT: fmov w8, s0
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- ; CHECK-GI-NEXT: add w0, w8, w0
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- ; CHECK-GI-NEXT: ret
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+ ; CHECK-LABEL: add_v4i16_v4i32_acc_sext:
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+ ; CHECK: // %bb.0: // %entry
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+ ; CHECK-NEXT: saddlv s0, v0.4h
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+ ; CHECK-NEXT: fmov w8, s0
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+ ; CHECK-NEXT: add w0, w8, w0
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+ ; CHECK-NEXT: ret
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entry:
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%xx = sext <4 x i16 > %x to <4 x i32 >
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%z = call i32 @llvm.vector.reduce.add.v4i32 (<4 x i32 > %xx )
@@ -1324,8 +1292,7 @@ define i32 @add_v4i8_v4i32_acc_zext(<4 x i8> %x, i32 %a) {
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; CHECK-SD-LABEL: add_v4i8_v4i32_acc_zext:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
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- ; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
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- ; CHECK-SD-NEXT: addv s0, v0.4s
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+ ; CHECK-SD-NEXT: uaddlv s0, v0.4h
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; CHECK-SD-NEXT: fmov w8, s0
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; CHECK-SD-NEXT: add w0, w8, w0
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; CHECK-SD-NEXT: ret
@@ -1402,22 +1369,13 @@ entry:
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}
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define zeroext i16 @add_v8i8_v8i16_acc_zext (<8 x i8 > %x , i16 %a ) {
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- ; CHECK-SD-LABEL: add_v8i8_v8i16_acc_zext:
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- ; CHECK-SD: // %bb.0: // %entry
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- ; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
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- ; CHECK-SD-NEXT: addv h0, v0.8h
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- ; CHECK-SD-NEXT: fmov w8, s0
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- ; CHECK-SD-NEXT: add w8, w8, w0
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- ; CHECK-SD-NEXT: and w0, w8, #0xffff
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- ; CHECK-SD-NEXT: ret
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- ;
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- ; CHECK-GI-LABEL: add_v8i8_v8i16_acc_zext:
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- ; CHECK-GI: // %bb.0: // %entry
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- ; CHECK-GI-NEXT: uaddlv h0, v0.8b
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- ; CHECK-GI-NEXT: fmov w8, s0
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- ; CHECK-GI-NEXT: add w8, w8, w0
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- ; CHECK-GI-NEXT: and w0, w8, #0xffff
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- ; CHECK-GI-NEXT: ret
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+ ; CHECK-LABEL: add_v8i8_v8i16_acc_zext:
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+ ; CHECK: // %bb.0: // %entry
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+ ; CHECK-NEXT: uaddlv h0, v0.8b
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+ ; CHECK-NEXT: fmov w8, s0
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+ ; CHECK-NEXT: add w8, w8, w0
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+ ; CHECK-NEXT: and w0, w8, #0xffff
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+ ; CHECK-NEXT: ret
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entry:
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%xx = zext <8 x i8 > %x to <8 x i16 >
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%z = call i16 @llvm.vector.reduce.add.v8i16 (<8 x i16 > %xx )
@@ -1426,22 +1384,13 @@ entry:
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}
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define signext i16 @add_v8i8_v8i16_acc_sext (<8 x i8 > %x , i16 %a ) {
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- ; CHECK-SD-LABEL: add_v8i8_v8i16_acc_sext:
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- ; CHECK-SD: // %bb.0: // %entry
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- ; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
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- ; CHECK-SD-NEXT: addv h0, v0.8h
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- ; CHECK-SD-NEXT: fmov w8, s0
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- ; CHECK-SD-NEXT: add w8, w8, w0
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- ; CHECK-SD-NEXT: sxth w0, w8
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- ; CHECK-SD-NEXT: ret
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- ;
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- ; CHECK-GI-LABEL: add_v8i8_v8i16_acc_sext:
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- ; CHECK-GI: // %bb.0: // %entry
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- ; CHECK-GI-NEXT: saddlv h0, v0.8b
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- ; CHECK-GI-NEXT: fmov w8, s0
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- ; CHECK-GI-NEXT: add w8, w8, w0
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- ; CHECK-GI-NEXT: sxth w0, w8
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- ; CHECK-GI-NEXT: ret
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+ ; CHECK-LABEL: add_v8i8_v8i16_acc_sext:
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+ ; CHECK: // %bb.0: // %entry
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+ ; CHECK-NEXT: saddlv h0, v0.8b
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+ ; CHECK-NEXT: fmov w8, s0
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+ ; CHECK-NEXT: add w8, w8, w0
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+ ; CHECK-NEXT: sxth w0, w8
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+ ; CHECK-NEXT: ret
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entry:
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%xx = sext <8 x i8 > %x to <8 x i16 >
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%z = call i16 @llvm.vector.reduce.add.v8i16 (<8 x i16 > %xx )
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