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IanTaylerLessa-armIanTaylerLessa-arm
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Merge branch 'llvm:main' into reduce-folding-overflow
2 parents 095f8be + 822aa5e commit c04ca68

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‎clang/lib/AST/ByteCode/Compiler.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1818,7 +1818,7 @@ bool Compiler<Emitter>::visitInitList(ArrayRef<const Expr *> Inits,
18181818
for (const Expr *Init : Inits) {
18191819
// Skip unnamed bitfields.
18201820
while (InitIndex < R->getNumFields() &&
1821-
R->getField(InitIndex)->Decl->isUnnamedBitField())
1821+
R->getField(InitIndex)->isUnnamedBitField())
18221822
++InitIndex;
18231823

18241824
if (std::optional<PrimType> T = classify(Init)) {
@@ -4084,7 +4084,7 @@ bool Compiler<Emitter>::visitZeroRecordInitializer(const Record *R,
40844084
assert(R);
40854085
// Fields
40864086
for (const Record::Field &Field : R->fields()) {
4087-
if (Field.Decl->isUnnamedBitField())
4087+
if (Field.isUnnamedBitField())
40884088
continue;
40894089

40904090
const Descriptor *D = Field.Desc;

‎clang/lib/AST/ByteCode/Pointer.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -720,6 +720,10 @@ IntPointer IntPointer::atOffset(const ASTContext &ASTCtx,
720720

721721
IntPointer IntPointer::baseCast(const ASTContext &ASTCtx,
722722
unsigned BaseOffset) const {
723+
if (!Desc) {
724+
assert(Value == 0);
725+
return *this;
726+
}
723727
const Record *R = Desc->ElemRecord;
724728
const Descriptor *BaseDesc = nullptr;
725729

‎clang/test/AST/ByteCode/records.cpp

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1771,3 +1771,19 @@ namespace RedeclaredCtor {
17711771
constexpr __sp_mut::__sp_mut(void *p) noexcept : __lx_(p) {}
17721772
constexpr __sp_mut muts = &mut_back[0];
17731773
}
1774+
1775+
namespace IntegralBaseCast {
1776+
class A {};
1777+
class B : public A {};
1778+
struct S {
1779+
B *a;
1780+
};
1781+
1782+
constexpr int f() {
1783+
S s{};
1784+
A *a = s.a;
1785+
return 0;
1786+
}
1787+
1788+
static_assert(f() == 0, "");
1789+
}

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

Lines changed: 121 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2811,6 +2811,17 @@ InstructionCost AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
28112811
BF16Tbl, ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT()))
28122812
return AdjustCost(Entry->Cost);
28132813

2814+
// Symbolic constants for the SVE sitofp/uitofp entries in the table below
2815+
// The cost of unpacking twice is artificially increased for now in order
2816+
// to avoid regressions against NEON, which will use tbl instructions directly
2817+
// instead of multiple layers of [s|u]unpk[lo|hi].
2818+
// We use the unpacks in cases where the destination type is illegal and
2819+
// requires splitting of the input, even if the input type itself is legal.
2820+
const unsigned int SVE_EXT_COST = 1;
2821+
const unsigned int SVE_FCVT_COST = 1;
2822+
const unsigned int SVE_UNPACK_ONCE = 4;
2823+
const unsigned int SVE_UNPACK_TWICE = 16;
2824+
28142825
static const TypeConversionCostTblEntry ConversionTbl[] = {
28152826
{ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1}, // xtn
28162827
{ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1}, // xtn
@@ -2936,6 +2947,42 @@ InstructionCost AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
29362947
{ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1},
29372948
{ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1},
29382949

2950+
// SVE: to nxv2f16
2951+
{ISD::SINT_TO_FP, MVT::nxv2f16, MVT::nxv2i8,
2952+
SVE_EXT_COST + SVE_FCVT_COST},
2953+
{ISD::SINT_TO_FP, MVT::nxv2f16, MVT::nxv2i16, SVE_FCVT_COST},
2954+
{ISD::SINT_TO_FP, MVT::nxv2f16, MVT::nxv2i32, SVE_FCVT_COST},
2955+
{ISD::SINT_TO_FP, MVT::nxv2f16, MVT::nxv2i64, SVE_FCVT_COST},
2956+
{ISD::UINT_TO_FP, MVT::nxv2f16, MVT::nxv2i8,
2957+
SVE_EXT_COST + SVE_FCVT_COST},
2958+
{ISD::UINT_TO_FP, MVT::nxv2f16, MVT::nxv2i16, SVE_FCVT_COST},
2959+
{ISD::UINT_TO_FP, MVT::nxv2f16, MVT::nxv2i32, SVE_FCVT_COST},
2960+
{ISD::UINT_TO_FP, MVT::nxv2f16, MVT::nxv2i64, SVE_FCVT_COST},
2961+
2962+
// SVE: to nxv4f16
2963+
{ISD::SINT_TO_FP, MVT::nxv4f16, MVT::nxv4i8,
2964+
SVE_EXT_COST + SVE_FCVT_COST},
2965+
{ISD::SINT_TO_FP, MVT::nxv4f16, MVT::nxv4i16, SVE_FCVT_COST},
2966+
{ISD::SINT_TO_FP, MVT::nxv4f16, MVT::nxv4i32, SVE_FCVT_COST},
2967+
{ISD::UINT_TO_FP, MVT::nxv4f16, MVT::nxv4i8,
2968+
SVE_EXT_COST + SVE_FCVT_COST},
2969+
{ISD::UINT_TO_FP, MVT::nxv4f16, MVT::nxv4i16, SVE_FCVT_COST},
2970+
{ISD::UINT_TO_FP, MVT::nxv4f16, MVT::nxv4i32, SVE_FCVT_COST},
2971+
2972+
// SVE: to nxv8f16
2973+
{ISD::SINT_TO_FP, MVT::nxv8f16, MVT::nxv8i8,
2974+
SVE_EXT_COST + SVE_FCVT_COST},
2975+
{ISD::SINT_TO_FP, MVT::nxv8f16, MVT::nxv8i16, SVE_FCVT_COST},
2976+
{ISD::UINT_TO_FP, MVT::nxv8f16, MVT::nxv8i8,
2977+
SVE_EXT_COST + SVE_FCVT_COST},
2978+
{ISD::UINT_TO_FP, MVT::nxv8f16, MVT::nxv8i16, SVE_FCVT_COST},
2979+
2980+
// SVE: to nxv16f16
2981+
{ISD::SINT_TO_FP, MVT::nxv16f16, MVT::nxv16i8,
2982+
SVE_UNPACK_ONCE + 2 * SVE_FCVT_COST},
2983+
{ISD::UINT_TO_FP, MVT::nxv16f16, MVT::nxv16i8,
2984+
SVE_UNPACK_ONCE + 2 * SVE_FCVT_COST},
2985+
29392986
// Complex: to v2f32
29402987
{ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3},
29412988
{ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3},
@@ -2944,18 +2991,56 @@ InstructionCost AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
29442991
{ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3},
29452992
{ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2},
29462993

2994+
// SVE: to nxv2f32
2995+
{ISD::SINT_TO_FP, MVT::nxv2f32, MVT::nxv2i8,
2996+
SVE_EXT_COST + SVE_FCVT_COST},
2997+
{ISD::SINT_TO_FP, MVT::nxv2f32, MVT::nxv2i16, SVE_FCVT_COST},
2998+
{ISD::SINT_TO_FP, MVT::nxv2f32, MVT::nxv2i32, SVE_FCVT_COST},
2999+
{ISD::SINT_TO_FP, MVT::nxv2f32, MVT::nxv2i64, SVE_FCVT_COST},
3000+
{ISD::UINT_TO_FP, MVT::nxv2f32, MVT::nxv2i8,
3001+
SVE_EXT_COST + SVE_FCVT_COST},
3002+
{ISD::UINT_TO_FP, MVT::nxv2f32, MVT::nxv2i16, SVE_FCVT_COST},
3003+
{ISD::UINT_TO_FP, MVT::nxv2f32, MVT::nxv2i32, SVE_FCVT_COST},
3004+
{ISD::UINT_TO_FP, MVT::nxv2f32, MVT::nxv2i64, SVE_FCVT_COST},
3005+
29473006
// Complex: to v4f32
29483007
{ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4},
29493008
{ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2},
29503009
{ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3},
29513010
{ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2},
29523011

3012+
// SVE: to nxv4f32
3013+
{ISD::SINT_TO_FP, MVT::nxv4f32, MVT::nxv4i8,
3014+
SVE_EXT_COST + SVE_FCVT_COST},
3015+
{ISD::SINT_TO_FP, MVT::nxv4f32, MVT::nxv4i16, SVE_FCVT_COST},
3016+
{ISD::SINT_TO_FP, MVT::nxv4f32, MVT::nxv4i32, SVE_FCVT_COST},
3017+
{ISD::UINT_TO_FP, MVT::nxv4f32, MVT::nxv4i8,
3018+
SVE_EXT_COST + SVE_FCVT_COST},
3019+
{ISD::UINT_TO_FP, MVT::nxv4f32, MVT::nxv4i16, SVE_FCVT_COST},
3020+
{ISD::SINT_TO_FP, MVT::nxv4f32, MVT::nxv4i32, SVE_FCVT_COST},
3021+
29533022
// Complex: to v8f32
29543023
{ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10},
29553024
{ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4},
29563025
{ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 10},
29573026
{ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4},
29583027

3028+
// SVE: to nxv8f32
3029+
{ISD::SINT_TO_FP, MVT::nxv8f32, MVT::nxv8i8,
3030+
SVE_EXT_COST + SVE_UNPACK_ONCE + 2 * SVE_FCVT_COST},
3031+
{ISD::SINT_TO_FP, MVT::nxv8f32, MVT::nxv8i16,
3032+
SVE_UNPACK_ONCE + 2 * SVE_FCVT_COST},
3033+
{ISD::UINT_TO_FP, MVT::nxv8f32, MVT::nxv8i8,
3034+
SVE_EXT_COST + SVE_UNPACK_ONCE + 2 * SVE_FCVT_COST},
3035+
{ISD::UINT_TO_FP, MVT::nxv8f32, MVT::nxv8i16,
3036+
SVE_UNPACK_ONCE + 2 * SVE_FCVT_COST},
3037+
3038+
// SVE: to nxv16f32
3039+
{ISD::SINT_TO_FP, MVT::nxv16f32, MVT::nxv16i8,
3040+
SVE_UNPACK_TWICE + 4 * SVE_FCVT_COST},
3041+
{ISD::UINT_TO_FP, MVT::nxv16f32, MVT::nxv16i8,
3042+
SVE_UNPACK_TWICE + 4 * SVE_FCVT_COST},
3043+
29593044
// Complex: to v16f32
29603045
{ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 21},
29613046
{ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 21},
@@ -2968,10 +3053,46 @@ InstructionCost AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
29683053
{ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4},
29693054
{ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2},
29703055

3056+
// SVE: to nxv2f64
3057+
{ISD::SINT_TO_FP, MVT::nxv2f64, MVT::nxv2i8,
3058+
SVE_EXT_COST + SVE_FCVT_COST},
3059+
{ISD::SINT_TO_FP, MVT::nxv2f64, MVT::nxv2i16, SVE_FCVT_COST},
3060+
{ISD::SINT_TO_FP, MVT::nxv2f64, MVT::nxv2i32, SVE_FCVT_COST},
3061+
{ISD::SINT_TO_FP, MVT::nxv2f64, MVT::nxv2i64, SVE_FCVT_COST},
3062+
{ISD::UINT_TO_FP, MVT::nxv2f64, MVT::nxv2i8,
3063+
SVE_EXT_COST + SVE_FCVT_COST},
3064+
{ISD::UINT_TO_FP, MVT::nxv2f64, MVT::nxv2i16, SVE_FCVT_COST},
3065+
{ISD::UINT_TO_FP, MVT::nxv2f64, MVT::nxv2i32, SVE_FCVT_COST},
3066+
{ISD::UINT_TO_FP, MVT::nxv2f64, MVT::nxv2i64, SVE_FCVT_COST},
3067+
29713068
// Complex: to v4f64
29723069
{ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 4},
29733070
{ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 4},
29743071

3072+
// SVE: to nxv4f64
3073+
{ISD::SINT_TO_FP, MVT::nxv4f64, MVT::nxv4i8,
3074+
SVE_EXT_COST + SVE_UNPACK_ONCE + 2 * SVE_FCVT_COST},
3075+
{ISD::SINT_TO_FP, MVT::nxv4f64, MVT::nxv4i16,
3076+
SVE_UNPACK_ONCE + 2 * SVE_FCVT_COST},
3077+
{ISD::SINT_TO_FP, MVT::nxv4f64, MVT::nxv4i32,
3078+
SVE_UNPACK_ONCE + 2 * SVE_FCVT_COST},
3079+
{ISD::UINT_TO_FP, MVT::nxv4f64, MVT::nxv4i8,
3080+
SVE_EXT_COST + SVE_UNPACK_ONCE + 2 * SVE_FCVT_COST},
3081+
{ISD::UINT_TO_FP, MVT::nxv4f64, MVT::nxv4i16,
3082+
SVE_UNPACK_ONCE + 2 * SVE_FCVT_COST},
3083+
{ISD::UINT_TO_FP, MVT::nxv4f64, MVT::nxv4i32,
3084+
SVE_UNPACK_ONCE + 2 * SVE_FCVT_COST},
3085+
3086+
// SVE: to nxv8f64
3087+
{ISD::SINT_TO_FP, MVT::nxv8f64, MVT::nxv8i8,
3088+
SVE_EXT_COST + SVE_UNPACK_TWICE + 4 * SVE_FCVT_COST},
3089+
{ISD::SINT_TO_FP, MVT::nxv8f64, MVT::nxv8i16,
3090+
SVE_UNPACK_TWICE + 4 * SVE_FCVT_COST},
3091+
{ISD::UINT_TO_FP, MVT::nxv8f64, MVT::nxv8i8,
3092+
SVE_EXT_COST + SVE_UNPACK_TWICE + 4 * SVE_FCVT_COST},
3093+
{ISD::UINT_TO_FP, MVT::nxv8f64, MVT::nxv8i16,
3094+
SVE_UNPACK_TWICE + 4 * SVE_FCVT_COST},
3095+
29753096
// LowerVectorFP_TO_INT
29763097
{ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1},
29773098
{ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1},

‎llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -133,7 +133,8 @@ class SMEAttrs {
133133
bool hasZT0State() const { return isNewZT0() || sharesZT0(); }
134134
bool requiresPreservingZT0(const SMEAttrs &Callee) const {
135135
return hasZT0State() && !Callee.sharesZT0() &&
136-
!Callee.hasAgnosticZAInterface();
136+
!Callee.hasAgnosticZAInterface() &&
137+
!(Callee.Bitmask & SME_ABI_Routine);
137138
}
138139
bool requiresDisablingZABeforeCall(const SMEAttrs &Callee) const {
139140
return hasZT0State() && !hasZAState() && Callee.hasPrivateZAInterface() &&

‎llvm/lib/Target/AMDGPU/AMDGPU.h

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -385,6 +385,12 @@ class SIInsertWaitcntsPass : public PassInfoMixin<SIInsertWaitcntsPass> {
385385
static bool isRequired() { return true; }
386386
};
387387

388+
class SIInsertHardClausesPass : public PassInfoMixin<SIInsertHardClausesPass> {
389+
public:
390+
PreservedAnalyses run(MachineFunction &MF,
391+
MachineFunctionAnalysisManager &MFAM);
392+
};
393+
388394
FunctionPass *createAMDGPUAnnotateUniformValuesLegacy();
389395

390396
ModulePass *createAMDGPUPrintfRuntimeBinding();
@@ -458,7 +464,7 @@ extern char &SIModeRegisterID;
458464
void initializeAMDGPUInsertDelayAluLegacyPass(PassRegistry &);
459465
extern char &AMDGPUInsertDelayAluID;
460466

461-
void initializeSIInsertHardClausesPass(PassRegistry &);
467+
void initializeSIInsertHardClausesLegacyPass(PassRegistry &);
462468
extern char &SIInsertHardClausesID;
463469

464470
void initializeSIInsertWaitcntsLegacyPass(PassRegistry &);

‎llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -111,6 +111,7 @@ MACHINE_FUNCTION_PASS("si-fix-vgpr-copies", SIFixVGPRCopiesPass())
111111
MACHINE_FUNCTION_PASS("si-fold-operands", SIFoldOperandsPass());
112112
MACHINE_FUNCTION_PASS("si-form-memory-clauses", SIFormMemoryClausesPass())
113113
MACHINE_FUNCTION_PASS("si-i1-copies", SILowerI1CopiesPass())
114+
MACHINE_FUNCTION_PASS("si-insert-hard-clauses", SIInsertHardClausesPass())
114115
MACHINE_FUNCTION_PASS("si-insert-waitcnts", SIInsertWaitcntsPass())
115116
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
116117
MACHINE_FUNCTION_PASS("si-lower-control-flow", SILowerControlFlowPass())
@@ -133,7 +134,6 @@ DUMMY_MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations", GCNPreRAOptimizations
133134
DUMMY_MACHINE_FUNCTION_PASS("amdgpu-rewrite-partial-reg-uses", GCNRewritePartialRegUsesPass())
134135
DUMMY_MACHINE_FUNCTION_PASS("amdgpu-set-wave-priority", AMDGPUSetWavePriorityPass())
135136

136-
DUMMY_MACHINE_FUNCTION_PASS("si-insert-hard-clauses", SIInsertHardClausesPass())
137137
DUMMY_MACHINE_FUNCTION_PASS("si-late-branch-lowering", SILateBranchLoweringPass())
138138
DUMMY_MACHINE_FUNCTION_PASS("si-pre-emit-peephole", SIPreEmitPeepholePass())
139139
// TODO: Move amdgpu-preload-kern-arg-prolog to MACHINE_FUNCTION_PASS since it

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -535,7 +535,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
535535
initializeAMDGPUUnifyMetadataPass(*PR);
536536
initializeSIAnnotateControlFlowLegacyPass(*PR);
537537
initializeAMDGPUInsertDelayAluLegacyPass(*PR);
538-
initializeSIInsertHardClausesPass(*PR);
538+
initializeSIInsertHardClausesLegacyPass(*PR);
539539
initializeSIInsertWaitcntsLegacyPass(*PR);
540540
initializeSIModeRegisterLegacyPass(*PR);
541541
initializeSIWholeQuadModeLegacyPass(*PR);

‎llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp

Lines changed: 35 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
3737
#include "llvm/ADT/SmallVector.h"
3838
#include "llvm/CodeGen/MachineFunctionPass.h"
39+
#include "llvm/CodeGen/MachinePassManager.h"
3940

4041
using namespace llvm;
4142

@@ -89,18 +90,10 @@ enum HardClauseType {
8990
HARDCLAUSE_ILLEGAL,
9091
};
9192

92-
class SIInsertHardClauses : public MachineFunctionPass {
93+
class SIInsertHardClauses {
9394
public:
94-
static char ID;
9595
const GCNSubtarget *ST = nullptr;
9696

97-
SIInsertHardClauses() : MachineFunctionPass(ID) {}
98-
99-
void getAnalysisUsage(AnalysisUsage &AU) const override {
100-
AU.setPreservesCFG();
101-
MachineFunctionPass::getAnalysisUsage(AU);
102-
}
103-
10497
HardClauseType getHardClauseType(const MachineInstr &MI) {
10598
if (MI.mayLoad() || (MI.mayStore() && ST->shouldClusterStores())) {
10699
if (ST->getGeneration() == AMDGPUSubtarget::GFX10) {
@@ -189,9 +182,7 @@ class SIInsertHardClauses : public MachineFunctionPass {
189182
return true;
190183
}
191184

192-
bool runOnMachineFunction(MachineFunction &MF) override {
193-
if (skipFunction(MF.getFunction()))
194-
return false;
185+
bool run(MachineFunction &MF) {
195186

196187
ST = &MF.getSubtarget<GCNSubtarget>();
197188
if (!ST->hasHardClauses())
@@ -265,11 +256,40 @@ class SIInsertHardClauses : public MachineFunctionPass {
265256
}
266257
};
267258

259+
class SIInsertHardClausesLegacy : public MachineFunctionPass {
260+
public:
261+
static char ID;
262+
SIInsertHardClausesLegacy() : MachineFunctionPass(ID) {}
263+
264+
bool runOnMachineFunction(MachineFunction &MF) override {
265+
if (skipFunction(MF.getFunction()))
266+
return false;
267+
268+
return SIInsertHardClauses().run(MF);
269+
}
270+
271+
void getAnalysisUsage(AnalysisUsage &AU) const override {
272+
AU.setPreservesCFG();
273+
MachineFunctionPass::getAnalysisUsage(AU);
274+
}
275+
};
276+
268277
} // namespace
269278

270-
char SIInsertHardClauses::ID = 0;
279+
PreservedAnalyses
280+
llvm::SIInsertHardClausesPass::run(MachineFunction &MF,
281+
MachineFunctionAnalysisManager &MFAM) {
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if (!SIInsertHardClauses().run(MF))
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return PreservedAnalyses::all();
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auto PA = getMachineFunctionPassPreservedAnalyses();
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PA.preserveSet<CFGAnalyses>();
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return PA;
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}
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char SIInsertHardClausesLegacy::ID = 0;
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char &llvm::SIInsertHardClausesID = SIInsertHardClauses::ID;
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char &llvm::SIInsertHardClausesID = SIInsertHardClausesLegacy::ID;
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INITIALIZE_PASS(SIInsertHardClauses, DEBUG_TYPE, "SI Insert Hard Clauses",
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INITIALIZE_PASS(SIInsertHardClausesLegacy, DEBUG_TYPE, "SI Insert Hard Clauses",
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false, false)

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