[AMDGPU] Set hasSideEffects=0 for SALU psuedos

Author: Aman Sharma

llvm/lib/Target/AMDGPU/SIInstructions.td

@@ -340,19 +340,27 @@ def S_SUB_U64_PSEUDO : SPseudoInstSI <
 
 def S_ADD_CO_PSEUDO : SPseudoInstSI <
   (outs SReg_32:$sdst, SSrc_i1:$scc_out), (ins SSrc_b32:$src0, SSrc_b32:$src1, SSrc_i1:$scc_in)
->;
+>{
+    let hasSideEffects = 0;
+}
 
 def S_SUB_CO_PSEUDO : SPseudoInstSI <
   (outs SReg_32:$sdst, SSrc_i1:$scc_out), (ins SSrc_b32:$src0, SSrc_b32:$src1, SSrc_i1:$scc_in)
->;
+>{
+    let hasSideEffects = 0;
+}
 
 def S_UADDO_PSEUDO : SPseudoInstSI <
   (outs SReg_32:$sdst, SSrc_i1:$scc_out), (ins SSrc_b32:$src0, SSrc_b32:$src1)
->;
+>{
+    let hasSideEffects = 0;
+}
 
 def S_USUBO_PSEUDO : SPseudoInstSI <
   (outs SReg_32:$sdst, SSrc_i1:$scc_out), (ins SSrc_b32:$src0, SSrc_b32:$src1)
->;
+>{
+    let hasSideEffects = 0;
+}
 
 let OtherPredicates = [HasShaderCyclesHiLoRegisters] in
 def GET_SHADERCYCLESHILO : SPseudoInstSI<

llvm/lib/Target/AMDGPU/SOPInstructions.td

@@ -665,12 +665,16 @@ let SubtargetPredicate = isGFX12Plus in {
   // The higher 32-bits of the inputs contain the sign extension bits.
   def S_MUL_I64_I32_PSEUDO : SPseudoInstSI <
     (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1)
-  >;
+  >{
+      let hasSideEffects = 0;
+  }
 
   // The higher 32-bits of the inputs are zero.
   def S_MUL_U64_U32_PSEUDO : SPseudoInstSI <
     (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1)
-  >;
+  >{
+    let hasSideEffects = 0;
+  }
 
 } // End SubtargetPredicate = isGFX12Plus