Skip to content

Commit c1049e4

Browse files
rampitecrampitec
authored
[AMDGPU] Correct VOP3P encoding. NFC. (#136005)
VOP3P encoding field was defined as 9 bit in GFX8/GFX9 and opcode was 7 bit, while it is 8 and 8 since GFX10. There are no changes to instructions, but it fixes difference with SP3 in terms of fields breakdown.
1 parent 8c83355 commit c1049e4

File tree

2 files changed

+37
-33
lines changed

2 files changed

+37
-33
lines changed

‎llvm/lib/Target/AMDGPU/VOP3PInstructions.td

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1686,7 +1686,7 @@ let WaveSizePredicate = isWave64, SubtargetPredicate = isGFX12Plus in {
16861686
// Begin Real Encodings
16871687
//===----------------------------------------------------------------------===//
16881688

1689-
class VOP3P_DPP16<bits<7> op, VOP_DPP_Pseudo ps, int subtarget,
1689+
class VOP3P_DPP16<bits<8> op, VOP_DPP_Pseudo ps, int subtarget,
16901690
string opName = ps.OpName>
16911691
: VOP3P_DPP<op, opName, ps.Pfl, 1>, SIMCInstr<ps.PseudoInstr, subtarget> {
16921692
let hasSideEffects = ps.hasSideEffects;
@@ -1699,7 +1699,7 @@ class VOP3P_DPP16<bits<7> op, VOP_DPP_Pseudo ps, int subtarget,
16991699
let IsPacked = ps.IsPacked;
17001700
}
17011701

1702-
class VOP3P_DPP8_Base<bits<7> op, VOP_Pseudo ps, string opName = ps.OpName>
1702+
class VOP3P_DPP8_Base<bits<8> op, VOP_Pseudo ps, string opName = ps.OpName>
17031703
: VOP3P_DPP8<op, opName, ps.Pfl> {
17041704
let hasSideEffects = ps.hasSideEffects;
17051705
let Defs = ps.Defs;
@@ -1714,14 +1714,14 @@ class VOP3P_DPP8_Base<bits<7> op, VOP_Pseudo ps, string opName = ps.OpName>
17141714
// GFX11, GFX12
17151715
//===----------------------------------------------------------------------===//
17161716

1717-
multiclass VOP3P_Real_Base<GFXGen Gen, bits<7> op, string backing_ps_name = NAME,
1717+
multiclass VOP3P_Real_Base<GFXGen Gen, bits<8> op, string backing_ps_name = NAME,
17181718
string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> {
17191719
def Gen.Suffix :
17201720
VOP3P_Real_Gen<!cast<VOP3P_Pseudo>(backing_ps_name), Gen, asmName>,
17211721
VOP3Pe_gfx11_gfx12<op, !cast<VOP3P_Pseudo>(backing_ps_name).Pfl>;
17221722
}
17231723

1724-
class VOP3PeWmma<bits<7> op, VOPProfile P, VOP3PWMMA_Profile WMMAP>
1724+
class VOP3PeWmma<bits<8> op, VOPProfile P, VOP3PWMMA_Profile WMMAP>
17251725
: VOP3Pe_gfx11_gfx12<op, P>{
17261726
// opsel
17271727
let Inst{11} = !cond(!eq(WMMAP.IndexType, 0) : 0,
@@ -1745,21 +1745,21 @@ class VOP3PeWmma<bits<7> op, VOPProfile P, VOP3PWMMA_Profile WMMAP>
17451745
let Inst{15} = !if(WMMAP.IsIU, clamp{0}, 0);
17461746
}
17471747

1748-
multiclass VOP3P_WMMA_Real_Base<GFXGen Gen, bits<7> op, VOP3PWMMA_Profile WMMAP,
1748+
multiclass VOP3P_WMMA_Real_Base<GFXGen Gen, bits<8> op, VOP3PWMMA_Profile WMMAP,
17491749
string backing_ps_name = NAME,
17501750
string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> {
17511751
def Gen.Suffix :
17521752
VOP3P_Real_Gen<!cast<VOP3P_Pseudo>(backing_ps_name), Gen, asmName>,
17531753
VOP3PeWmma<op, !cast<VOP3P_Pseudo>(backing_ps_name).Pfl, WMMAP>;
17541754
}
17551755

1756-
multiclass VOP3P_Real_WMMA_gfx12 <bits<7> op, VOP3PWMMA_Profile WMMAP> {
1756+
multiclass VOP3P_Real_WMMA_gfx12 <bits<8> op, VOP3PWMMA_Profile WMMAP> {
17571757
let WaveSizePredicate = isWave32, DecoderNamespace = "GFX12" in {
17581758
defm _twoaddr : VOP3P_WMMA_Real_Base <GFX12Gen, op, WMMAP>;
17591759
}
17601760
}
17611761

1762-
multiclass VOP3P_Real_WMMA_gfx12w64 <bits<7> op, VOP3PWMMA_Profile WMMAP> {
1762+
multiclass VOP3P_Real_WMMA_gfx12w64 <bits<8> op, VOP3PWMMA_Profile WMMAP> {
17631763
let WaveSizePredicate = isWave64, DecoderNamespace = "GFX12W64" in {
17641764
defm _twoaddr : VOP3P_WMMA_Real_Base <GFX12Gen, op, WMMAP>;
17651765
}
@@ -1814,7 +1814,7 @@ defm V_SWMMAC_F32_16X16X32_FP8_BF8_w64 : VOP3P_Real_WMMA_gfx12w64 <0x058, F32_FP
18141814
defm V_SWMMAC_F32_16X16X32_BF8_FP8_w64 : VOP3P_Real_WMMA_gfx12w64 <0x059, F32_FP8BF8_SWMMAC_w64>;
18151815
defm V_SWMMAC_F32_16X16X32_BF8_BF8_w64 : VOP3P_Real_WMMA_gfx12w64 <0x05a, F32_FP8BF8_SWMMAC_w64>;
18161816

1817-
multiclass VOP3P_Real_with_name<GFXGen Gen, bits<7> op,
1817+
multiclass VOP3P_Real_with_name<GFXGen Gen, bits<8> op,
18181818
string backing_ps_name = NAME,
18191819
string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> {
18201820
defvar ps = !cast<VOP3P_Pseudo>(backing_ps_name);
@@ -1828,7 +1828,7 @@ multiclass VOP3P_Real_with_name<GFXGen Gen, bits<7> op,
18281828
}
18291829
}
18301830

1831-
multiclass VOP3P_Real_dpp<GFXGen Gen, bits<7> op, string backing_ps_name = NAME,
1831+
multiclass VOP3P_Real_dpp<GFXGen Gen, bits<8> op, string backing_ps_name = NAME,
18321832
string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> {
18331833
defvar ps = !cast<VOP3P_Pseudo>(backing_ps_name);
18341834
def _dpp#Gen.Suffix
@@ -1840,7 +1840,7 @@ multiclass VOP3P_Real_dpp<GFXGen Gen, bits<7> op, string backing_ps_name = NAME,
18401840
}
18411841
}
18421842

1843-
multiclass VOP3P_Real_dpp8<GFXGen Gen, bits<7> op, string backing_ps_name = NAME,
1843+
multiclass VOP3P_Real_dpp8<GFXGen Gen, bits<8> op, string backing_ps_name = NAME,
18441844
string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> {
18451845
defvar ps = !cast<VOP3P_Pseudo>(backing_ps_name);
18461846
def _dpp8#Gen.Suffix : VOP3P_DPP8_Base<op, ps> {
@@ -1850,7 +1850,7 @@ multiclass VOP3P_Real_dpp8<GFXGen Gen, bits<7> op, string backing_ps_name = NAME
18501850
}
18511851
}
18521852

1853-
multiclass VOP3P_Realtriple<GFXGen Gen, bits<7> op, string backing_ps_name = NAME,
1853+
multiclass VOP3P_Realtriple<GFXGen Gen, bits<8> op, string backing_ps_name = NAME,
18541854
string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic>
18551855
: VOP3P_Real_Base<Gen, op, backing_ps_name, asmName>,
18561856
VOP3P_Real_dpp<Gen, op, backing_ps_name, asmName>,
@@ -1860,9 +1860,9 @@ multiclass VOP3P_Realtriple<GFXGen Gen, bits<7> op, string backing_ps_name = NAM
18601860
// GFX12
18611861
//===----------------------------------------------------------------------===//
18621862

1863-
multiclass VOP3P_Real_gfx12<bits<7> op> : VOP3P_Real_Base<GFX12Gen, op>;
1863+
multiclass VOP3P_Real_gfx12<bits<8> op> : VOP3P_Real_Base<GFX12Gen, op>;
18641864

1865-
multiclass VOP3P_Real_with_name_gfx12<bits<7> op,
1865+
multiclass VOP3P_Real_with_name_gfx12<bits<8> op,
18661866
string backing_ps_name = NAME,
18671867
string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> :
18681868
VOP3P_Real_with_name<GFX12Gen, op, backing_ps_name, asmName>;
@@ -1882,7 +1882,7 @@ defm V_DOT4_F32_BF8_BF8 : VOP3P_Realtriple<GFX12Gen, 0x27>;
18821882
// GFX11
18831883
//===----------------------------------------------------------------------===//
18841884

1885-
multiclass VOP3P_Real_gfx11_gfx12<bits<7> op> :
1885+
multiclass VOP3P_Real_gfx11_gfx12<bits<8> op> :
18861886
VOP3P_Real_Base<GFX11Gen, op>, VOP3P_Real_Base<GFX12Gen, op>;
18871887

18881888
defm V_DOT4_I32_IU8 : VOP3P_Real_gfx11_gfx12<0x16>;
@@ -1894,7 +1894,7 @@ let AssemblerPredicate = isGFX11Plus in {
18941894
def : AMDGPUMnemonicAlias<"v_dot8_i32_i4", "v_dot8_i32_iu4">;
18951895
}
18961896

1897-
multiclass VOP3P_Real_WMMA <bits<7> op> {
1897+
multiclass VOP3P_Real_WMMA <bits<8> op> {
18981898
let WaveSizePredicate = isWave32, DecoderNamespace = "GFX11" in {
18991899
defm _twoaddr_w32 : VOP3P_Real_Base <GFX11Gen, op>;
19001900
}
@@ -1916,7 +1916,7 @@ defm V_WMMA_I32_16X16X16_IU4 : VOP3P_Real_WMMA <0x045>;
19161916

19171917
multiclass VOP3P_Real_vi<bits<7> op> {
19181918
def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
1919-
VOP3Pe <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
1919+
VOP3Pe_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
19201920
let AssemblerPredicate = HasVOP3PInsts;
19211921
let DecoderNamespace = "GFX8";
19221922
let VOP3P = 1;
@@ -2257,19 +2257,19 @@ defm V_PK_MOV_B32 : VOP3P_Real_vi <0x33>;
22572257
//===----------------------------------------------------------------------===//
22582258

22592259
let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1 in {
2260-
multiclass VOP3P_Real_gfx10<bits<7> op> {
2260+
multiclass VOP3P_Real_gfx10<bits<8> op> {
22612261
def _gfx10 : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.GFX10>,
22622262
VOP3Pe_gfx10 <op, !cast<VOP3P_Pseudo>(NAME).Pfl>;
22632263
}
22642264
} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1
22652265

2266-
multiclass VOP3P_Real_gfx10_gfx11<bits<7> op> :
2266+
multiclass VOP3P_Real_gfx10_gfx11<bits<8> op> :
22672267
VOP3P_Real_gfx10<op>, VOP3P_Real_Base<GFX11Gen, op>;
22682268

2269-
multiclass VOP3P_Real_gfx10_gfx11_gfx12<bits<7> op> :
2269+
multiclass VOP3P_Real_gfx10_gfx11_gfx12<bits<8> op> :
22702270
VOP3P_Real_gfx10_gfx11<op>, VOP3P_Real_Base<GFX12Gen, op>;
22712271

2272-
multiclass VOP3P_Real_gfx10_gfx11_gfx12_Triple<bits<7> op> :
2272+
multiclass VOP3P_Real_gfx10_gfx11_gfx12_Triple<bits<8> op> :
22732273
VOP3P_Real_gfx10<op>, VOP3P_Realtriple<GFX11Gen, op>,
22742274
VOP3P_Realtriple<GFX12Gen, op>;
22752275

‎llvm/lib/Target/AMDGPU/VOPInstructions.td

Lines changed: 17 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -427,7 +427,7 @@ class VOP3be <VOPProfile P> : Enc64 {
427427
let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0);
428428
}
429429

430-
class VOP3Pe <bits<7> op, VOPProfile P> : Enc64 {
430+
class VOP3Pe <VOPProfile P> : Enc64 {
431431
bits<8> vdst;
432432
bits<4> src0_modifiers;
433433
bits<9> src0;
@@ -452,8 +452,6 @@ class VOP3Pe <bits<7> op, VOPProfile P> : Enc64 {
452452

453453
let Inst{15} = !if(P.HasClamp, clamp{0}, 0);
454454

455-
let Inst{22-16} = op;
456-
let Inst{31-23} = 0x1a7; //encoding
457455
let Inst{40-32} = !if(P.HasSrc0, src0, 0);
458456
let Inst{49-41} = !if(P.HasSrc1, src1, 0);
459457
let Inst{58-50} = !if(P.HasSrc2, src2, 0);
@@ -577,11 +575,17 @@ class VOP3PXe <bits<7> op, VOPProfile MFMAPfl, bit acc_cd = 0> : Enc128, VOP3Pe_
577575
let Inst{127-125} = !if(MFMAPfl.HasSrc1, blgp, 0);
578576
}
579577

580-
class VOP3Pe_gfx10 <bits<7> op, VOPProfile P> : VOP3Pe<op, P> {
581-
let Inst{31-23} = 0x198; //encoding
578+
class VOP3Pe_vi <bits<7> op, VOPProfile P> : VOP3Pe<P> {
579+
let Inst{22-16} = op;
580+
let Inst{31-23} = 0x1a7; //encoding
582581
}
583582

584-
class VOP3Pe_gfx11_gfx12<bits<7> op, VOPProfile P> : VOP3Pe_gfx10<op, P>;
583+
class VOP3Pe_gfx10 <bits<8> op, VOPProfile P> : VOP3Pe<P> {
584+
let Inst{23-16} = op;
585+
let Inst{31-24} = 0xcc; //encoding
586+
}
587+
588+
class VOP3Pe_gfx11_gfx12<bits<8> op, VOPProfile P> : VOP3Pe_gfx10<op, P>;
585589

586590
class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> {
587591
let Inst{25-17} = op;
@@ -902,7 +906,7 @@ class VOP3_DPPe_Common_t16<bits<10> op, VOPProfile P> : VOP3_DPPe_Common_Base<op
902906
let Inst{58-50} = !if(P.HasSrc2, src2{8-0}, 0);
903907
}
904908

905-
class VOP3P_DPPe_Common_Base<bits<7> op, VOPProfile P> : Enc96 {
909+
class VOP3P_DPPe_Common_Base<bits<8> op, VOPProfile P> : Enc96 {
906910
bits<4> src0_modifiers;
907911
bits<4> src1_modifiers;
908912
bits<4> src2_modifiers;
@@ -917,16 +921,16 @@ class VOP3P_DPPe_Common_Base<bits<7> op, VOPProfile P> : Enc96 {
917921
let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2)
918922
let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, !if(P.IsDOT, 1, ?)); // op_sel_hi(2)
919923
let Inst{15} = !if(P.HasClamp, clamp{0}, 0);
920-
let Inst{22-16} = op;
921-
let Inst{31-23} = 0x198; // encoding
924+
let Inst{23-16} = op;
925+
let Inst{31-24} = 0xcc; // encoding
922926
let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, !if(P.IsDOT, 1, ?)); // op_sel_hi(0)
923927
let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, !if(P.IsDOT, 1, ?)); // op_sel_hi(1)
924928
let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo)
925929
let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo)
926930
let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo)
927931
}
928932

929-
class VOP3P_DPPe_Common<bits<7> op, VOPProfile P> : VOP3P_DPPe_Common_Base<op, P> {
933+
class VOP3P_DPPe_Common<bits<8> op, VOPProfile P> : VOP3P_DPPe_Common_Base<op, P> {
930934
bits<8> vdst;
931935
bits<9> src1;
932936
bits<9> src2;
@@ -936,7 +940,7 @@ class VOP3P_DPPe_Common<bits<7> op, VOPProfile P> : VOP3P_DPPe_Common_Base<op, P
936940
let Inst{58-50} = !if(P.HasSrc2, src2, 0);
937941
}
938942

939-
class VOP3P_DPPe_Common_t16<bits<7> op, VOPProfile P> : VOP3P_DPPe_Common_Base<op, P> {
943+
class VOP3P_DPPe_Common_t16<bits<8> op, VOPProfile P> : VOP3P_DPPe_Common_Base<op, P> {
940944
bits<11> vdst;
941945
bits<11> src1;
942946
bits<11> src2;
@@ -1107,7 +1111,7 @@ class VOP3_DPP_t16<bits<10> op, string OpName, VOPProfile P, bit IsDPP16,
11071111
VOP3_DPP_Enc_t16<op, P, IsDPP16> {
11081112
}
11091113

1110-
class VOP3P_DPP <bits<7> op, string OpName, VOPProfile P, bit IsDPP16,
1114+
class VOP3P_DPP <bits<8> op, string OpName, VOPProfile P, bit IsDPP16,
11111115
dag InsDPP = !if(IsDPP16, P.InsVOP3DPP16, P.InsVOP3DPP),
11121116
string AsmDPP = !if(IsDPP16, P.AsmVOP3DPP16, P.AsmVOP3DPP)> :
11131117
VOP3_DPP_Base<OpName, P, IsDPP16, InsDPP, AsmDPP>, VOP3P_DPPe_Common<op, P>,
@@ -1201,7 +1205,7 @@ class VOP3_DPP8_Enc_t16 <bits<10> op, VOPProfile P> :
12011205
class VOP3_DPP8_t16<bits<10> op, string OpName, VOPProfile P> :
12021206
VOP3_DPP8_Base<OpName, P>, VOP3_DPP8_Enc_t16<op, P>;
12031207

1204-
class VOP3P_DPP8<bits<7> op, string OpName, VOPProfile P> :
1208+
class VOP3P_DPP8<bits<8> op, string OpName, VOPProfile P> :
12051209
VOP3_DPP8_Base<OpName, P>, VOP3P_DPPe_Common<op, P>,
12061210
VOP3_DPP8e_Fields {
12071211

0 commit comments

Comments
 (0)