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Revert "[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X)."
This reverts commit 673d68c. This hadn't been reviewed yet.
1 parent d1899da commit c1cef11

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4 files changed

+4
-24
lines changed

4 files changed

+4
-24
lines changed

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 0 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1069,8 +1069,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
10691069
setTargetDAGCombine(ISD::OR);
10701070
setTargetDAGCombine(ISD::XOR);
10711071
setTargetDAGCombine(ISD::ANY_EXTEND);
1072-
if (Subtarget.hasStdExtZfh())
1073-
setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
10741072
if (Subtarget.hasStdExtF()) {
10751073
setTargetDAGCombine(ISD::ZERO_EXTEND);
10761074
setTargetDAGCombine(ISD::FP_TO_SINT);
@@ -7357,18 +7355,6 @@ static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG) {
73577355
return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false);
73587356
}
73597357

7360-
static SDValue performSIGN_EXTEND_INREG(SDNode *N, SelectionDAG &DAG) {
7361-
SDValue Src = N->getOperand(0);
7362-
7363-
// Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X)
7364-
if (Src.getOpcode() == RISCVISD::FMV_X_ANYEXTH &&
7365-
cast<VTSDNode>(N->getOperand(1))->getVT().bitsGE(MVT::i16))
7366-
return DAG.getNode(RISCVISD::FMV_X_SIGNEXTH, SDLoc(N), N->getValueType(0),
7367-
Src.getOperand(0));
7368-
7369-
return SDValue();
7370-
}
7371-
73727358
// Attempt to turn ANY_EXTEND into SIGN_EXTEND if the input to the ANY_EXTEND
73737359
// has users that require SIGN_EXTEND and the SIGN_EXTEND can be done for free
73747360
// by an instruction like ADDW/SUBW/MULW. Without this the ANY_EXTEND would be
@@ -7955,8 +7941,6 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
79557941
return performORCombine(N, DAG, Subtarget);
79567942
case ISD::XOR:
79577943
return performXORCombine(N, DAG);
7958-
case ISD::SIGN_EXTEND_INREG:
7959-
return performSIGN_EXTEND_INREG(N, DAG);
79607944
case ISD::ANY_EXTEND:
79617945
return performANY_EXTENDCombine(N, DCI, Subtarget);
79627946
case ISD::ZERO_EXTEND:
@@ -10352,7 +10336,6 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
1035210336
NODE_NAME_CASE(FSR)
1035310337
NODE_NAME_CASE(FMV_H_X)
1035410338
NODE_NAME_CASE(FMV_X_ANYEXTH)
10355-
NODE_NAME_CASE(FMV_X_SIGNEXTH)
1035610339
NODE_NAME_CASE(FMV_W_X_RV64)
1035710340
NODE_NAME_CASE(FMV_X_ANYEXTW_RV64)
1035810341
NODE_NAME_CASE(FCVT_X)

llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -75,15 +75,13 @@ enum NodeType : unsigned {
7575
//
7676
// FMV_H_X matches the semantics of the FMV.H.X.
7777
// FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
78-
// FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.
7978
// FMV_W_X_RV64 matches the semantics of the FMV.W.X.
8079
// FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
8180
//
8281
// This is a more convenient semantic for producing dagcombines that remove
8382
// unnecessary GPR->FPR->GPR moves.
8483
FMV_H_X,
8584
FMV_X_ANYEXTH,
86-
FMV_X_SIGNEXTH,
8785
FMV_W_X_RV64,
8886
FMV_X_ANYEXTW_RV64,
8987
// FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and

llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -17,15 +17,13 @@
1717

1818
def SDT_RISCVFMV_H_X
1919
: SDTypeProfile<1, 1, [SDTCisVT<0, f16>, SDTCisVT<1, XLenVT>]>;
20-
def SDT_RISCVFMV_X_EXTH
20+
def SDT_RISCVFMV_X_ANYEXTH
2121
: SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisVT<1, f16>]>;
2222

2323
def riscv_fmv_h_x
2424
: SDNode<"RISCVISD::FMV_H_X", SDT_RISCVFMV_H_X>;
2525
def riscv_fmv_x_anyexth
26-
: SDNode<"RISCVISD::FMV_X_ANYEXTH", SDT_RISCVFMV_X_EXTH>;
27-
def riscv_fmv_x_signexth
28-
: SDNode<"RISCVISD::FMV_X_SIGNEXTH", SDT_RISCVFMV_X_EXTH>;
26+
: SDNode<"RISCVISD::FMV_X_ANYEXTH", SDT_RISCVFMV_X_ANYEXTH>;
2927

3028
//===----------------------------------------------------------------------===//
3129
// Instructions
@@ -301,7 +299,6 @@ def : Pat<(any_fpextend FPR16:$rs1), (FCVT_S_H FPR16:$rs1)>;
301299
// Moves (no conversion)
302300
def : Pat<(riscv_fmv_h_x GPR:$src), (FMV_H_X GPR:$src)>;
303301
def : Pat<(riscv_fmv_x_anyexth FPR16:$src), (FMV_X_H FPR16:$src)>;
304-
def : Pat<(riscv_fmv_x_signexth FPR16:$src), (FMV_X_H FPR16:$src)>;
305302
} // Predicates = [HasStdExtZfhOrZfhmin]
306303

307304
let Predicates = [HasStdExtZfh, IsRV32] in {

llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,8 @@ define signext i16 @bcvt_f16_to_sext_i16(half %a, half %b) nounwind {
7979
; RV64IZFH: # %bb.0:
8080
; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
8181
; RV64IZFH-NEXT: fmv.x.h a0, ft0
82+
; RV64IZFH-NEXT: slli a0, a0, 48
83+
; RV64IZFH-NEXT: srai a0, a0, 48
8284
; RV64IZFH-NEXT: ret
8385
%1 = fadd half %a, %b
8486
%2 = bitcast half %1 to i16

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