scalable vectorized G_ADD, G_SUB, G_AND, G_OR, G_XOR don't fall back to DAGISel

Author: jiahanxie353

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -19874,11 +19874,13 @@ unsigned RISCVTargetLowering::getCustomCtpopCost(EVT VT,
 }
 
 bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
-  // At the moment, the only scalable instruction GISel knows how to lower is
-  // ret with scalable argument.
 
-  if (Inst.getType()->isScalableTy())
-    return true;
+  // GISel support is in progress or complete for G_ADD, G_SUB, G_AND, G_OR, and
+  // G_XOR.
+  unsigned Op = Inst.getOpcode();
+  if (Op == Instruction::Add || Op == Instruction::Sub ||
+      Op == Instruction::And || Op == Instruction::Or || Op == Instruction::Xor)
+    return false;
 
   for (unsigned i = 0; i < Inst.getNumOperands(); ++i)
     if (Inst.getOperand(i)->getType()->isScalableTy() &&

llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-alu.ll

@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-before=legalizer -simplify-mir < %s | FileCheck %s --check-prefixes=CHECK,RV32I %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-before=legalizer -simplify-mir < %s | FileCheck %s --check-prefixes=CHECK,RV64I %s
+
+define void @add_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
+  ; CHECK-LABEL: name: add_nxv2i32
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $v8, $v9
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   PseudoRET
+  %c = add <vscale x 2 x i32> %a, %b
+  ret void
+}
+
+define void @sub_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
+  ; CHECK-LABEL: name: sub_nxv2i32
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $v8, $v9
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   PseudoRET
+  %c = sub <vscale x 2 x i32> %a, %b
+  ret void
+}
+
+define void @and_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
+  ; CHECK-LABEL: name: and_nxv2i32
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $v8, $v9
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   PseudoRET
+  %c = and <vscale x 2 x i32> %a, %b
+  ret void
+}
+
+define void @or_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
+  ; CHECK-LABEL: name: or_nxv2i32
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $v8, $v9
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   PseudoRET
+  %c = or <vscale x 2 x i32> %a, %b
+  ret void
+}
+
+define void @xor_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
+  ; CHECK-LABEL: name: xor_nxv2i32
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $v8, $v9
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   PseudoRET
+  %c = xor <vscale x 2 x i32> %a, %b
+  ret void
+}