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[Exegesis][RISCV] Add initial RVV support (#128767)
This patch adds initial vector extension support to RISC-V's exegesis. The strategy here is to enumerate all RVV _pseudo_ opcodes as their MC opcode counterparts are kind of useless under this circumstance. We also enumerate all possible VTYPE operands in each CodeTemplate configuration. Various of MachineFunction Passes are used for post processing the snippets, like inserting VSETVLI instructions. See https://llvm.org/devmtg/2024-10/slides/techtalk/Hsu-RVV-Exegesis.pdf for more technical details.
1 parent b923f6c commit c253e5c

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-52
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‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

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@@ -432,7 +432,44 @@ enum RoundingMode {
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RNE = 1,
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RDN = 2,
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ROD = 3,
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Invalid
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};
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inline static StringRef roundingModeToString(RoundingMode RndMode) {
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switch (RndMode) {
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default:
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llvm_unreachable("Unknown vector fixed-point rounding mode");
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case RISCVVXRndMode::RNU:
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return "rnu";
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case RISCVVXRndMode::RNE:
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return "rne";
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case RISCVVXRndMode::RDN:
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return "rdn";
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case RISCVVXRndMode::ROD:
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return "rod";
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}
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}
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inline static RoundingMode stringToRoundingMode(StringRef Str) {
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return StringSwitch<RoundingMode>(Str)
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.Case("rnu", RISCVVXRndMode::RNU)
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.Case("rne", RISCVVXRndMode::RNE)
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.Case("rdn", RISCVVXRndMode::RDN)
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.Case("rod", RISCVVXRndMode::ROD)
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.Default(RISCVVXRndMode::Invalid);
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}
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inline static bool isValidRoundingMode(unsigned Mode) {
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switch (Mode) {
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default:
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return false;
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case RISCVVXRndMode::RNU:
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case RISCVVXRndMode::RNE:
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case RISCVVXRndMode::RDN:
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case RISCVVXRndMode::ROD:
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return true;
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}
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}
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} // namespace RISCVVXRndMode
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//===----------------------------------------------------------------------===//

‎llvm/test/tools/llvm-exegesis/RISCV/rvv/eligible-inst.test

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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency \
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# RUN: --opcode-name=PseudoVCOMPRESS_VM_M2_E8,PseudoVCPOP_M_B32 | \
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# RUN: FileCheck %s --allow-empty --check-prefix=LATENCY
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=inverse_throughput \
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# RUN: --opcode-name=PseudoVCOMPRESS_VM_M2_E8,PseudoVCPOP_M_B32 \
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# RUN: --min-instructions=100 | \
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# RUN: FileCheck %s --check-prefix=RTHROUGHPUT1
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency \
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# RUN: --opcode-name=PseudoVRGATHEREI16_VV_M2_E32_M1,PseudoVRGATHER_VI_M2,PseudoVRGATHER_VV_M8_E32,PseudoVRGATHER_VX_M4 | \
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# RUN: FileCheck %s --allow-empty --check-prefix=LATENCY
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=inverse_throughput \
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# RUN: --opcode-name=PseudoVRGATHEREI16_VV_M2_E32_M1,PseudoVRGATHER_VI_M2,PseudoVRGATHER_VV_M8_E32,PseudoVRGATHER_VX_M4 \
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# RUN: --min-instructions=100 | \
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# RUN: FileCheck %s --check-prefix=RTHROUGHPUT2
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency \
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# RUN: --opcode-name=PseudoVSLIDE1UP_VX_M1,PseudoVSLIDEUP_VI_M2,PseudoVSLIDEUP_VX_M2 | \
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# RUN: FileCheck %s --allow-empty --check-prefix=LATENCY
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=inverse_throughput \
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# RUN: --opcode-name=PseudoVSLIDE1UP_VX_M1,PseudoVSLIDEUP_VI_M2,PseudoVSLIDEUP_VX_M2 \
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# RUN: --min-instructions=100 | \
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# RUN: FileCheck %s --check-prefix=RTHROUGHPUT3
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency \
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# RUN: --opcode-name=PseudoVNCLIPU_WI_M2,PseudoVNSRA_WI_M2,PseudoVNSRL_WI_M2 | \
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# RUN: FileCheck %s --allow-empty --check-prefix=LATENCY
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=inverse_throughput \
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# RUN: --opcode-name=PseudoVNCLIPU_WI_M2,PseudoVNSRA_WI_M2,PseudoVNSRL_WI_M2 \
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# RUN: --min-instructions=100 | \
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# RUN: FileCheck %s --check-prefix=RTHROUGHPUT4
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# These instructions are only eligible under the inverse throughput mode.
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# LATENCY-NOT: PseudoVCOMPRESS_VM_M2_E8
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# LATENCY-NOT: PseudoVCPOP_M_B32
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# LATENCY-NOT: PseudoVRGATHEREI16_VV_M2_E32_M1
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# LATENCY-NOT: PseudoVRGATHER_VI_M2
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# LATENCY-NOT: PseudoVRGATHER_VV_M8_E32
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# LATENCY-NOT: PseudoVRGATHER_VX_M4
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# LATENCY-NOT: PseudoVSLIDE1UP_VX_M1
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# LATENCY-NOT: PseudoVSLIDEUP_VI_M2
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# LATENCY-NOT: PseudoVSLIDEUP_VX_M2
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# LATENCY-NOT: PseudoVNCLIPU_WI_M2
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# LATENCY-NOT: PseudoVNSRA_WI_M2
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# LATENCY-NOT: PseudoVNSRL_WI_M2
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# RTHROUGHPUT1: PseudoVCOMPRESS_VM_M2_E8
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# RTHROUGHPUT1: PseudoVCPOP_M_B32
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# RTHROUGHPUT2: PseudoVRGATHEREI16_VV_M2_E32_M1
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# RTHROUGHPUT2: PseudoVRGATHER_VI_M2
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# RTHROUGHPUT2: PseudoVRGATHER_VV_M8_E32
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# RTHROUGHPUT2: PseudoVRGATHER_VX_M4
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# RTHROUGHPUT3: PseudoVSLIDE1UP_VX_M1
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# RTHROUGHPUT3: PseudoVSLIDEUP_VI_M2
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# RTHROUGHPUT3: PseudoVSLIDEUP_VX_M2
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# RTHROUGHPUT4: PseudoVNCLIPU_WI_M2
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# RTHROUGHPUT4: PseudoVNSRA_WI_M2
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# RTHROUGHPUT4: PseudoVNSRL_WI_M2

‎llvm/test/tools/llvm-exegesis/RISCV/rvv/explicit-sew.test

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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency --opcode-name=PseudoVFWREDUSUM_VS_M1_E32 \
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# RUN: --max-configs-per-opcode=1000 --min-instructions=100 | FileCheck %s
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# Make sure none of the config has SEW other than e32
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# CHECK: PseudoVFWREDUSUM_VS_M1_E32
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# CHECK: SEW: e32
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# CHECK-NOT: SEW: e{{(8|16|64)}}

‎llvm/test/tools/llvm-exegesis/RISCV/rvv/filter.test

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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=inverse_throughput --opcode-name=PseudoVNCLIPU_WX_M1_MASK \
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# RUN: --riscv-filter-config='vtype = {VXRM: rod, AVL: VLMAX, SEW: e(8|16), Policy: ta/mu}' --max-configs-per-opcode=1000 --min-instructions=100 | FileCheck %s
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# CHECK: config: 'vtype = {VXRM: rod, AVL: VLMAX, SEW: e8, Policy: ta/mu}'
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# CHECK: config: 'vtype = {VXRM: rod, AVL: VLMAX, SEW: e16, Policy: ta/mu}'
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# CHECK-NOT: config: 'vtype = {VXRM: rod, AVL: VLMAX, SEW: e(32|64), Policy: ta/mu}'

‎llvm/test/tools/llvm-exegesis/RISCV/rvv/reduction.test

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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-p670 -benchmark-phase=assemble-measured-code --mode=latency --opcode-name=PseudoVWREDSUMU_VS_M8_E32 --min-instructions=100 | \
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# RUN: FileCheck %s
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# Make sure reduction ops don't have alias between vd and vs1
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# CHECK: instructions:
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# CHECK-NEXT: PseudoVWREDSUMU_VS_M8_E32
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# CHECK-NOT: V[[REG:[0-9]+]] V[[REG]] V{{[0-9]+}}M8 V[[REG]]

‎llvm/test/tools/llvm-exegesis/RISCV/rvv/self-aliasing.test

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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency --opcode-name=PseudoVXOR_VX_M4 --min-instructions=100 | \
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# RUN: FileCheck %s
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# Make sure all def / use operands are the same in latency mode.
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# CHECK: instructions:
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# CHECK-NEXT: PseudoVXOR_VX_M4 V[[REG:[0-9]+]]M4 V[[REG]]M4 V[[REG]]M4 X{{.*}}

‎llvm/test/tools/llvm-exegesis/RISCV/rvv/skip-rm.test

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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency --opcode-name=PseudoVAADDU_VV_M1 \
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# RUN: --riscv-enumerate-rounding-modes=false --max-configs-per-opcode=1000 --min-instructions=100 | FileCheck %s --check-prefix=VX
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency --opcode-name=PseudoVFADD_VFPR16_M1_E16 \
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# RUN: --riscv-enumerate-rounding-modes=false --max-configs-per-opcode=1000 --min-instructions=100 | FileCheck %s --check-prefix=FP
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# VX: PseudoVAADDU_VV_M1
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# VX: VXRM: rnu
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# VX-NOT: VXRM: {{(rne|rdn|rod)}}
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# FP: PseudoVFADD_VFPR16_M1_E16
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# FP: FRM: dyn
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# FP-NOT: FRM: {{(rtz|rdn|rup|rmm|rne)}}

‎llvm/test/tools/llvm-exegesis/RISCV/rvv/valid-sew-zvk.test

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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-p670 -benchmark-phase=assemble-measured-code --mode=inverse_throughput \
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# RUN: --opcode-name=PseudoVAESDF_VS_M1_M1 --max-configs-per-opcode=1000 --min-instructions=100 | \
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# RUN: FileCheck %s --check-prefix=ZVK
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-p670 -benchmark-phase=assemble-measured-code --mode=inverse_throughput \
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# RUN: --opcode-name=PseudoVGHSH_VV_M1 --max-configs-per-opcode=1000 --min-instructions=100 | \
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# RUN: FileCheck %s --check-prefix=ZVK
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-p670 -benchmark-phase=assemble-measured-code --mode=inverse_throughput \
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# RUN: --opcode-name=PseudoVSM4K_VI_M1 --max-configs-per-opcode=1000 --min-instructions=100 | \
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# RUN: FileCheck %s --check-prefix=ZVK
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-p670 -benchmark-phase=assemble-measured-code --mode=inverse_throughput \
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# RUN: --opcode-name=PseudoVSM3C_VI_M2 --max-configs-per-opcode=1000 --min-instructions=100 | \
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# RUN: FileCheck %s --check-prefix=ZVK
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-p670 -benchmark-phase=assemble-measured-code --mode=inverse_throughput \
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# RUN: --opcode-name=PseudoVSHA2MS_VV_M1_E32 --max-configs-per-opcode=1000 --min-instructions=100 | \
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# RUN: FileCheck %s --allow-empty --check-prefix=ZVKNH
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-p670 -benchmark-phase=assemble-measured-code --mode=inverse_throughput \
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# RUN: --opcode-name=PseudoVSHA2MS_VV_M2_E64 --max-configs-per-opcode=1000 --min-instructions=100 | \
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# RUN: FileCheck %s --allow-empty --check-prefix=ZVKNH
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-p670 -benchmark-phase=assemble-measured-code --mode=inverse_throughput \
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# RUN: --opcode-name=PseudoVSM3C_VI_M1 --max-configs-per-opcode=1000 --min-instructions=100 | \
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# RUN: FileCheck %s --allow-empty --check-prefix=EMPTY
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# Most vector crypto only supports SEW=32, except Zvknhb which also supports SEW=64
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# ZVK-NOT: SEW: e{{(8|16)}}
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# ZVK: SEW: e32
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# ZVK-NOT: SEW: e64
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# ZVKNH(A|B) can either have SEW=32 (EGW=128) or SEW=64 (EGW=256)
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# ZVKNH-NOT: SEW: e{{(8|16)}}
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# ZVKNH: SEW: e{{(32|64)}}
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# EMPTY-NOT: SEW: e{{(8|16|32|64)}}

‎llvm/test/tools/llvm-exegesis/RISCV/rvv/valid-sew.test

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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency --opcode-name=PseudoVMUL_VV_MF4_MASK \
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# RUN: --max-configs-per-opcode=1000 --min-instructions=100 | FileCheck %s --check-prefix=FRAC-LMUL
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency \
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# RUN: --opcode-name=PseudoVFADD_VFPR16_M1_E16,PseudoVFADD_VV_M2_E16,PseudoVFCLASS_V_MF2 --max-configs-per-opcode=1000 --min-instructions=100 | \
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# RUN: FileCheck %s --check-prefix=FP
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=inverse_throughput \
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# RUN: --opcode-name=PseudoVSEXT_VF8_M2,PseudoVZEXT_VF8_M2 --max-configs-per-opcode=1000 --min-instructions=100 | \
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# RUN: FileCheck %s --check-prefix=VEXT
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-p470 -benchmark-phase=assemble-measured-code --mode=latency \
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# RUN: --opcode-name=PseudoVFREDUSUM_VS_M1_E16 --max-configs-per-opcode=1000 --min-instructions=100 | \
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# RUN: FileCheck %s --check-prefix=VFRED --allow-empty
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# Make sure only the supported SEWs are generated for fractional LMUL.
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# FRAC-LMUL: PseudoVMUL_VV_MF4_MASK
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# FRAC-LMUL: SEW: e8
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# FRAC-LMUL: SEW: e16
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# FRAC-LMUL-NOT: SEW: e{{(32|64)}}
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# Make sure only SEWs that are equal to the supported FLEN are generated
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# FP: PseudoVFADD_VFPR16_M1_E16
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# FP-NOT: SEW: e8
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# FP: PseudoVFADD_VV_M2_E16
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# FP-NOT: SEW: e8
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# FP: PseudoVFCLASS_V_MF2
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# FP-NOT: SEW: e8
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# VS/ZEXT can only operate on SEW that will not lead to invalid EEW on the
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# source operand.
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# VEXT: PseudoVSEXT_VF8_M2
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# VEXT-NOT: SEW: e8
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# VEXT-NOT: SEW: e16
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# VEXT-NOT: SEW: e32
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# VEXT: SEW: e64
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# VEXT: PseudoVZEXT_VF8_M2
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# VEXT-NOT: SEW: e8
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# VEXT-NOT: SEW: e16
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# VEXT-NOT: SEW: e32
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# VEXT: SEW: e64
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# P470 doesn't have Zvfh so 16-bit vfredusum shouldn't exist
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# VFRED-NOT: PseudoVFREDUSUM_VS_M1_E16

‎llvm/test/tools/llvm-exegesis/RISCV/rvv/vlmax-only.test

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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency --opcode-name=PseudoVFWREDUSUM_VS_M1_E32 \
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# RUN: --riscv-vlmax-for-vl --max-configs-per-opcode=1000 --min-instructions=100 | FileCheck %s
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# Only allow VLMAX for AVL when -riscv-vlmax-for-vl is present
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# CHECK: PseudoVFWREDUSUM_VS_M1_E32
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# CHECK: AVL: VLMAX
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# CHECK-NOT: AVL: {{(simm5|<MCOperand: .*>)}}

‎llvm/test/tools/llvm-exegesis/RISCV/rvv/vtype-rm-setup.test

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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency --opcode-name=PseudoVFWREDUSUM_VS_M1_E32 \
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# RUN: --max-configs-per-opcode=1 --min-instructions=100 --dump-object-to-disk=%t.o > %t.txt
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# RUN: llvm-objdump --triple=riscv64 -d %t.o | FileCheck %s --check-prefix=VFWREDUSUM
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# RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency --opcode-name=PseudoVSSRL_VX_MF4 \
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# RUN: --max-configs-per-opcode=1 --min-instructions=100 --dump-object-to-disk=%t.o > %t.txt
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# RUN: llvm-objdump --triple=riscv64 -d %t.o | FileCheck %s --check-prefix=VSSRL
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# Make sure the correct VSETVL / VXRM write / FRM write instructions are generated
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# VFWREDUSUM: vsetvli {{.*}}, zero, e32, m1, tu, ma
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# VFWREDUSUM: fsrmi {{.*}}, 0x0
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# VSSRL: vsetvli {{.*}}, zero, e8, mf4, tu, ma
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# VSSRL: csrwi vxrm, 0x0

‎llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp

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@@ -50,6 +50,8 @@ bool Operand::isTied() const { return TiedToIndex.has_value(); }
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bool Operand::isVariable() const { return VariableIndex.has_value(); }
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bool Operand::isEarlyClobber() const { return IsEarlyClobber; }
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bool Operand::isMemory() const {
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return isExplicit() &&
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getExplicitOperandInfo().OperandType == MCOI::OPERAND_MEMORY;
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Operand Operand;
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Operand.Index = OpIndex;
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Operand.IsDef = (OpIndex < Description->getNumDefs());
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Operand.IsEarlyClobber =
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(Description->getOperandConstraint(OpIndex, MCOI::EARLY_CLOBBER) != -1);
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// TODO(gchatelet): Handle isLookupPtrRegClass.
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if (OpInfo.RegClass >= 0)
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Operand.Tracker = &RATC.getRegisterClass(OpInfo.RegClass);

‎llvm/tools/llvm-exegesis/lib/MCInstrDescView.h

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@@ -72,6 +72,7 @@ struct Operand {
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bool isVariable() const;
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bool isMemory() const;
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bool isImmediate() const;
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bool isEarlyClobber() const;
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unsigned getIndex() const;
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unsigned getTiedToIndex() const;
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unsigned getVariableIndex() const;
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// Please use the accessors above and not the following fields.
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std::optional<uint8_t> Index;
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bool IsDef = false;
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bool IsEarlyClobber = false;
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const RegisterAliasingTracker *Tracker = nullptr; // Set for Register Op.
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const MCOperandInfo *Info = nullptr; // Set for Explicit Op.
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std::optional<uint8_t> TiedToIndex; // Set for Reg&Explicit Op.
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Instruction &operator=(const Instruction &) = delete;
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Instruction &operator=(Instruction &&) = delete;
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unsigned getOpcode() const { return Description.getOpcode(); }
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// Returns the Operand linked to this Variable.
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// In case the Variable is tied, the primary (i.e. Def) Operand is returned.
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const Operand &getPrimaryOperand(const Variable &Var) const;

‎llvm/tools/llvm-exegesis/lib/RISCV/CMakeLists.txt

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add_llvm_library(LLVMExegesisRISCV
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DISABLE_LLVM_LINK_LLVM_DYLIB
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STATIC
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RISCVExegesisPreprocessing.cpp
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RISCVExegesisPostprocessing.cpp
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Target.cpp
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DEPENDS

‎llvm/tools/llvm-exegesis/lib/RISCV/RISCVExegesisPasses.h

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//===- RISCVExegesisPasses.h - RISC-V specific Exegesis Passes --*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TOOLS_EXEGESIS_LIB_RISCV_RISCVEXEGESISPASSES_H
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#define LLVM_TOOLS_EXEGESIS_LIB_RISCV_RISCVEXEGESISPASSES_H
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namespace llvm {
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class FunctionPass;
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namespace exegesis {
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FunctionPass *createRISCVPreprocessingPass();
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FunctionPass *createRISCVPostprocessingPass();
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} // namespace exegesis
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} // namespace llvm
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#endif

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