Skip to content

Commit c27b628

Browse files
committed
[mlir][ArmSME] Add rewrites to swap extract of extend
In mixed matmul lowering (e.g., i8 to i32) we're seeing the following sequence: %0 = arith.extsi %src : vector<4x[8]xi8> to vector<4x[8]xi32> %1 = vector.extract %0[0] : vector<[8]xi32> from vector<4x[8]xi32> %lhs = vector.scalable.extract %1[0] : vector<[4]xi32> from vector<[8]xi32> ... (same for rhs) %2 = vector.outerproduct %lhs, %rhs, %acc vector<[4]xi32>, vector<[4]xi32> // x4 chained by accumulator This chain of 4 outer products can be fused into a single 4-way widening variant but the pass doesn't match on the IR, as it expects the source of the inputs to be an extend and it can't look through the extracts. This patch fixes this with two rewrites that swaps extract(extend) into extend(extract). Related to #78975, #79288.
1 parent 75c4339 commit c27b628

File tree

2 files changed

+141
-0
lines changed

2 files changed

+141
-0
lines changed

mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp

Lines changed: 101 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -338,6 +338,105 @@ struct LegalizeTransferWriteOpsByDecomposition
338338
}
339339
};
340340

341+
// Shuffles arith extend ops after vector.extract op.
342+
//
343+
// This transforms IR like:
344+
// %0 = arith.extsi %src : vector<4x[8]xi8> to vector<4x[8]xi32>
345+
// %1 = vector.extract %0[0] : vector<[8]xi32> from vector<4x[8]xi32>
346+
// Into:
347+
// %0 = vector.extract %src[0] : vector<[8]xi8> from vector<4x[8]xi8>
348+
// %1 = arith.extsi %0 : vector<[8]xi8> to vector<[8]xi32>
349+
//
350+
// This enables outer product fusion in the `-arm-sme-outer-product-fusion`
351+
// pass when the result is the input to an outer product.
352+
struct SwapVectorExtractOfArithExtend
353+
: public OpRewritePattern<vector::ExtractOp> {
354+
using OpRewritePattern::OpRewritePattern;
355+
356+
LogicalResult matchAndRewrite(vector::ExtractOp extractOp,
357+
PatternRewriter &rewriter) const override {
358+
VectorType resultType = llvm::dyn_cast<VectorType>(extractOp.getType());
359+
if (!resultType)
360+
return rewriter.notifyMatchFailure(extractOp,
361+
"extracted type is not a vector type");
362+
363+
auto numScalableDims = llvm::count(resultType.getScalableDims(), true);
364+
if (numScalableDims != 1)
365+
return rewriter.notifyMatchFailure(
366+
extractOp, "extracted type is not a 1-D scalable vector type");
367+
368+
auto *extendOp = extractOp.getVector().getDefiningOp();
369+
if (!isa_and_present<arith::ExtSIOp, arith::ExtUIOp, arith::ExtFOp>(
370+
extendOp))
371+
return rewriter.notifyMatchFailure(extractOp,
372+
"extract not from extend op");
373+
374+
auto loc = extractOp.getLoc();
375+
StringAttr extendOpName = extendOp->getName().getIdentifier();
376+
Value extendSource = extendOp->getOperand(0);
377+
378+
// Create new extract from source of extend.
379+
Value newExtract = rewriter.create<vector::ExtractOp>(
380+
loc, extendSource, extractOp.getMixedPosition());
381+
382+
// Extend new extract to original result type.
383+
Operation *newExtend =
384+
rewriter.create(loc, extendOpName, Value(newExtract), resultType);
385+
386+
rewriter.replaceOp(extractOp, newExtend->getResult(0));
387+
388+
return success();
389+
}
390+
};
391+
392+
// Shuffles arith extend ops after vector.scalable.extract op.
393+
//
394+
// This transforms IR like:
395+
// %0 = arith.extsi %src : vector<[8]xi8> to vector<[8]xi32>
396+
// %1 = vector.scalable.extract %0[0] : vector<[4]xi32> from vector<[8]xi32>
397+
// Into:
398+
// %0 = vector.scalable.extract %src[0] : vector<[4]xi8> from vector<[8]xi8>
399+
// %1 = arith.extsi %0 : vector<[4]xi8> to vector<[4]xi32>
400+
//
401+
// This enables outer product fusion in the `-arm-sme-outer-product-fusion`
402+
// pass when the result is the input to an outer product.
403+
struct SwapVectorScalableExtractOfArithExtend
404+
: public OpRewritePattern<vector::ScalableExtractOp> {
405+
using OpRewritePattern::OpRewritePattern;
406+
407+
LogicalResult matchAndRewrite(vector::ScalableExtractOp extractOp,
408+
PatternRewriter &rewriter) const override {
409+
auto *extendOp = extractOp.getSource().getDefiningOp();
410+
if (!isa_and_present<arith::ExtSIOp, arith::ExtUIOp, arith::ExtFOp>(
411+
extendOp))
412+
return rewriter.notifyMatchFailure(extractOp,
413+
"extract not from extend op");
414+
415+
auto loc = extractOp.getLoc();
416+
VectorType resultType = extractOp.getResultVectorType();
417+
418+
Value extendSource = extendOp->getOperand(0);
419+
StringAttr extendOpName = extendOp->getName().getIdentifier();
420+
VectorType extendSourceVectorType =
421+
cast<VectorType>(extendSource.getType());
422+
423+
// Create new extract from source of extend.
424+
VectorType extractResultVectorType =
425+
VectorType::Builder(resultType)
426+
.setElementType(extendSourceVectorType.getElementType());
427+
Value newExtract = rewriter.create<vector::ScalableExtractOp>(
428+
loc, extractResultVectorType, extendSource, extractOp.getPos());
429+
430+
// Extend new extract to original result type.
431+
Operation *newExtend =
432+
rewriter.create(loc, extendOpName, Value(newExtract), resultType);
433+
434+
rewriter.replaceOp(extractOp, newExtend->getResult(0));
435+
436+
return success();
437+
}
438+
};
439+
341440
struct VectorLegalizationPass
342441
: public arm_sme::impl::VectorLegalizationBase<VectorLegalizationPass> {
343442
void runOnOperation() override {
@@ -358,6 +457,8 @@ struct VectorLegalizationPass
358457
return success();
359458
});
360459

460+
patterns.add<SwapVectorExtractOfArithExtend,
461+
SwapVectorScalableExtractOfArithExtend>(context);
361462
// Note: High benefit to ensure masked outer products are lowered first.
362463
patterns.add<LegalizeMaskedVectorOuterProductOpsByDecomposition>(
363464
converter, context, 1024);

mlir/test/Dialect/ArmSME/vector-legalization.mlir

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -266,3 +266,43 @@ func.func @transpose_f32_scalable_4x16_via_write(%src: memref<?x?xf32>, %dest: m
266266
vector.transfer_write %0, %dest[%c0, %c0] {permutation_map = #transpose, in_bounds = [true, true]} : vector<[4]x[16]xf32>, memref<?x?xf32>
267267
return
268268
}
269+
270+
// -----
271+
272+
// CHECK-LABEL: @extract_from_arith_ext(
273+
// CHECK-SAME: %[[SRC:.*]]: vector<4x[8]xi8>
274+
// CHECK: %[[EXTRACT:.*]] = vector.extract %[[SRC]][0] : vector<[8]xi8> from vector<4x[8]xi8>
275+
// CHECK: %[[EXTEND:.*]] = arith.extsi %[[EXTRACT]] : vector<[8]xi8> to vector<[8]xi32>
276+
// CHECK: return %[[EXTEND]]
277+
func.func @extract_from_arith_ext(%src: vector<4x[8]xi8>) -> vector<[8]xi32> {
278+
%0 = arith.extsi %src : vector<4x[8]xi8> to vector<4x[8]xi32>
279+
%1 = vector.extract %0[0] : vector<[8]xi32> from vector<4x[8]xi32>
280+
return %1 : vector<[8]xi32>
281+
}
282+
283+
// -----
284+
285+
// CHECK-LABEL: @non_constant_extract_from_arith_ext(
286+
// CHECK-SAME: %[[SRC:[a-z0-9]+]]: vector<4x[8]xi8>,
287+
// CHECK-SAME: %[[DIM:[a-z0-9]+]]: index
288+
// CHECK: %[[EXTRACT:.*]] = vector.extract %[[SRC]][%[[DIM]]] : vector<[8]xi8> from vector<4x[8]xi8>
289+
// CHECK: %[[EXTEND:.*]] = arith.extsi %[[EXTRACT]] : vector<[8]xi8> to vector<[8]xi32>
290+
// CHECK: return %[[EXTEND]]
291+
func.func @non_constant_extract_from_arith_ext(%src: vector<4x[8]xi8>, %dim: index) -> vector<[8]xi32> {
292+
%0 = arith.extsi %src : vector<4x[8]xi8> to vector<4x[8]xi32>
293+
%1 = vector.extract %0[%dim] : vector<[8]xi32> from vector<4x[8]xi32>
294+
return %1 : vector<[8]xi32>
295+
}
296+
297+
// -----
298+
299+
// CHECK-LABEL: @scalable_extract_from_arith_ext(
300+
// CHECK-SAME: %[[SRC:.*]]: vector<[8]xi8>
301+
// CHECK: %[[EXTRACT:.*]] = vector.scalable.extract %[[SRC]][0] : vector<[4]xi8> from vector<[8]xi8>
302+
// CHECK: %[[EXTEND:.*]] = arith.extsi %[[EXTRACT]] : vector<[4]xi8> to vector<[4]xi32>
303+
// CHECK: return %[[EXTEND]]
304+
func.func @scalable_extract_from_arith_ext(%src: vector<[8]xi8>) -> vector<[4]xi32> {
305+
%0 = arith.extsi %src : vector<[8]xi8> to vector<[8]xi32>
306+
%1 = vector.scalable.extract %0[0] : vector<[4]xi32> from vector<[8]xi32>
307+
return %1 : vector<[4]xi32>
308+
}

0 commit comments

Comments
 (0)