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kosarevkosarev
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[AMDGPU][NFC] Remove unused operand types. (#139062)
1 parent ea7e23c commit c290f48

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8 files changed

+10
-94
lines changed

8 files changed

+10
-94
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 4 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1954,21 +1954,17 @@ static const fltSemantics *getOpFltSemantics(uint8_t OperandType) {
19541954
// representation of the constant truncated to the 16 LSBs should be used.
19551955
case AMDGPU::OPERAND_REG_IMM_INT16:
19561956
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
1957-
case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
19581957
case AMDGPU::OPERAND_REG_IMM_INT32:
19591958
case AMDGPU::OPERAND_REG_IMM_FP32:
19601959
case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
19611960
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
19621961
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
19631962
case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
19641963
case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
1965-
case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
19661964
case AMDGPU::OPERAND_REG_IMM_V2FP32:
1967-
case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
19681965
case AMDGPU::OPERAND_REG_IMM_V2INT32:
19691966
case AMDGPU::OPERAND_REG_IMM_V2INT16:
19701967
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
1971-
case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
19721968
case AMDGPU::OPERAND_KIMM32:
19731969
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
19741970
return &APFloat::IEEEsingle();
@@ -1982,17 +1978,13 @@ static const fltSemantics *getOpFltSemantics(uint8_t OperandType) {
19821978
case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
19831979
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
19841980
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
1985-
case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
1986-
case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
19871981
case AMDGPU::OPERAND_REG_IMM_V2FP16:
19881982
case AMDGPU::OPERAND_KIMM16:
19891983
return &APFloat::IEEEhalf();
19901984
case AMDGPU::OPERAND_REG_IMM_BF16:
19911985
case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED:
19921986
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
19931987
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
1994-
case AMDGPU::OPERAND_REG_INLINE_AC_BF16:
1995-
case AMDGPU::OPERAND_REG_INLINE_AC_V2BF16:
19961988
case AMDGPU::OPERAND_REG_IMM_V2BF16:
19971989
return &APFloat::BFloat();
19981990
default:
@@ -2315,8 +2307,6 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23152307
case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED:
23162308
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
23172309
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
2318-
case AMDGPU::OPERAND_REG_INLINE_AC_BF16:
2319-
case AMDGPU::OPERAND_REG_INLINE_AC_V2BF16:
23202310
case AMDGPU::OPERAND_REG_IMM_V2BF16:
23212311
if (AsmParser->hasInv2PiInlineImm() && Literal == 0x3fc45f306725feed) {
23222312
// This is the 1/(2*pi) which is going to be truncated to bf16 with the
@@ -2343,15 +2333,9 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23432333
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
23442334
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
23452335
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
2346-
case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
2347-
case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
2348-
case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
2349-
case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
23502336
case AMDGPU::OPERAND_REG_IMM_V2INT16:
23512337
case AMDGPU::OPERAND_REG_IMM_V2FP16:
2352-
case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
23532338
case AMDGPU::OPERAND_REG_IMM_V2FP32:
2354-
case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
23552339
case AMDGPU::OPERAND_REG_IMM_V2INT32:
23562340
case AMDGPU::OPERAND_KIMM32:
23572341
case AMDGPU::OPERAND_KIMM16:
@@ -2394,9 +2378,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23942378
case AMDGPU::OPERAND_REG_IMM_V2BF16:
23952379
case AMDGPU::OPERAND_REG_IMM_V2FP16:
23962380
case AMDGPU::OPERAND_REG_IMM_V2FP32:
2397-
case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
23982381
case AMDGPU::OPERAND_REG_IMM_V2INT32:
2399-
case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
24002382
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
24012383
if (isSafeTruncation(Val, 32) &&
24022384
AMDGPU::isInlinableLiteral32(static_cast<int32_t>(Val),
@@ -2430,7 +2412,6 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24302412

24312413
case AMDGPU::OPERAND_REG_IMM_INT16:
24322414
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
2433-
case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
24342415
if (isSafeTruncation(Val, 16) &&
24352416
AMDGPU::isInlinableIntLiteral(static_cast<int16_t>(Val))) {
24362417
Inst.addOperand(MCOperand::createImm(Lo_32(Val)));
@@ -2445,7 +2426,6 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24452426
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
24462427
case AMDGPU::OPERAND_REG_IMM_FP16:
24472428
case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
2448-
case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
24492429
if (isSafeTruncation(Val, 16) &&
24502430
AMDGPU::isInlinableLiteralFP16(static_cast<int16_t>(Val),
24512431
AsmParser->hasInv2PiInlineImm())) {
@@ -2461,7 +2441,6 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24612441
case AMDGPU::OPERAND_REG_IMM_BF16:
24622442
case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED:
24632443
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
2464-
case AMDGPU::OPERAND_REG_INLINE_AC_BF16:
24652444
if (isSafeTruncation(Val, 16) &&
24662445
AMDGPU::isInlinableLiteralBF16(static_cast<int16_t>(Val),
24672446
AsmParser->hasInv2PiInlineImm())) {
@@ -2474,15 +2453,13 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24742453
setImmKindLiteral();
24752454
return;
24762455

2477-
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
2478-
case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: {
2456+
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: {
24792457
assert(isSafeTruncation(Val, 16));
24802458
assert(AMDGPU::isInlinableIntLiteral(static_cast<int16_t>(Val)));
24812459
Inst.addOperand(MCOperand::createImm(Val));
24822460
return;
24832461
}
2484-
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
2485-
case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: {
2462+
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: {
24862463
assert(isSafeTruncation(Val, 16));
24872464
assert(AMDGPU::isInlinableLiteralFP16(static_cast<int16_t>(Val),
24882465
AsmParser->hasInv2PiInlineImm()));
@@ -2491,8 +2468,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24912468
return;
24922469
}
24932470

2494-
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
2495-
case AMDGPU::OPERAND_REG_INLINE_AC_V2BF16: {
2471+
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16: {
24962472
assert(isSafeTruncation(Val, 16));
24972473
assert(AMDGPU::isInlinableLiteralBF16(static_cast<int16_t>(Val),
24982474
AsmParser->hasInv2PiInlineImm()));
@@ -3623,34 +3599,28 @@ bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,
36233599
case 2: {
36243600
const unsigned OperandType = Desc.operands()[OpIdx].OperandType;
36253601
if (OperandType == AMDGPU::OPERAND_REG_IMM_INT16 ||
3626-
OperandType == AMDGPU::OPERAND_REG_INLINE_C_INT16 ||
3627-
OperandType == AMDGPU::OPERAND_REG_INLINE_AC_INT16)
3602+
OperandType == AMDGPU::OPERAND_REG_INLINE_C_INT16)
36283603
return AMDGPU::isInlinableLiteralI16(Val, hasInv2PiInlineImm());
36293604

36303605
if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2INT16 ||
3631-
OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2INT16 ||
36323606
OperandType == AMDGPU::OPERAND_REG_IMM_V2INT16)
36333607
return AMDGPU::isInlinableLiteralV2I16(Val);
36343608

36353609
if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2FP16 ||
3636-
OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2FP16 ||
36373610
OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16)
36383611
return AMDGPU::isInlinableLiteralV2F16(Val);
36393612

36403613
if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2BF16 ||
3641-
OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2BF16 ||
36423614
OperandType == AMDGPU::OPERAND_REG_IMM_V2BF16)
36433615
return AMDGPU::isInlinableLiteralV2BF16(Val);
36443616

36453617
if (OperandType == AMDGPU::OPERAND_REG_IMM_FP16 ||
36463618
OperandType == AMDGPU::OPERAND_REG_INLINE_C_FP16 ||
3647-
OperandType == AMDGPU::OPERAND_REG_INLINE_AC_FP16 ||
36483619
OperandType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED)
36493620
return AMDGPU::isInlinableLiteralFP16(Val, hasInv2PiInlineImm());
36503621

36513622
if (OperandType == AMDGPU::OPERAND_REG_IMM_BF16 ||
36523623
OperandType == AMDGPU::OPERAND_REG_INLINE_C_BF16 ||
3653-
OperandType == AMDGPU::OPERAND_REG_INLINE_AC_BF16 ||
36543624
OperandType == AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED)
36553625
return AMDGPU::isInlinableLiteralBF16(Val, hasInv2PiInlineImm());
36563626

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -510,20 +510,17 @@ void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm, uint8_t OpType,
510510
switch (OpType) {
511511
case AMDGPU::OPERAND_REG_IMM_V2INT16:
512512
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
513-
case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
514513
if (printImmediateFloat32(Imm, STI, O))
515514
return;
516515
break;
517516
case AMDGPU::OPERAND_REG_IMM_V2FP16:
518517
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
519-
case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
520518
if (isUInt<16>(Imm) &&
521519
printImmediateFP16(static_cast<uint16_t>(Imm), STI, O))
522520
return;
523521
break;
524522
case AMDGPU::OPERAND_REG_IMM_V2BF16:
525523
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
526-
case AMDGPU::OPERAND_REG_INLINE_AC_V2BF16:
527524
if (isUInt<16>(Imm) &&
528525
printImmediateBFloat16(static_cast<uint16_t>(Imm), STI, O))
529526
return;
@@ -725,8 +722,6 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
725722
case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
726723
case AMDGPU::OPERAND_REG_IMM_V2INT32:
727724
case AMDGPU::OPERAND_REG_IMM_V2FP32:
728-
case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
729-
case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
730725
case MCOI::OPERAND_IMMEDIATE:
731726
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
732727
printImmediate32(Op.getImm(), STI, O);
@@ -741,18 +736,15 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
741736
printImmediate64(Op.getImm(), STI, O, true);
742737
break;
743738
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
744-
case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
745739
case AMDGPU::OPERAND_REG_IMM_INT16:
746740
printImmediateInt16(Op.getImm(), STI, O);
747741
break;
748742
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
749-
case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
750743
case AMDGPU::OPERAND_REG_IMM_FP16:
751744
case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
752745
printImmediateF16(Op.getImm(), STI, O);
753746
break;
754747
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
755-
case AMDGPU::OPERAND_REG_INLINE_AC_BF16:
756748
case AMDGPU::OPERAND_REG_IMM_BF16:
757749
case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED:
758750
printImmediateBF16(Op.getImm(), STI, O);
@@ -761,11 +753,8 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
761753
case AMDGPU::OPERAND_REG_IMM_V2BF16:
762754
case AMDGPU::OPERAND_REG_IMM_V2FP16:
763755
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
764-
case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
765756
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
766757
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
767-
case AMDGPU::OPERAND_REG_INLINE_AC_V2BF16:
768-
case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
769758
printImmediateV216(Op.getImm(), OpTy, STI, O);
770759
break;
771760
case MCOI::OPERAND_UNKNOWN:

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -280,8 +280,6 @@ AMDGPUMCCodeEmitter::getLitEncoding(const MCOperand &MO,
280280
case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
281281
case AMDGPU::OPERAND_REG_IMM_V2INT32:
282282
case AMDGPU::OPERAND_REG_IMM_V2FP32:
283-
case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
284-
case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
285283
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
286284
return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
287285

@@ -294,40 +292,34 @@ AMDGPUMCCodeEmitter::getLitEncoding(const MCOperand &MO,
294292

295293
case AMDGPU::OPERAND_REG_IMM_INT16:
296294
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
297-
case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
298295
return getLit16IntEncoding(static_cast<uint32_t>(Imm), STI);
299296

300297
case AMDGPU::OPERAND_REG_IMM_FP16:
301298
case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
302299
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
303-
case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
304300
// FIXME Is this correct? What do inline immediates do on SI for f16 src
305301
// which does not have f16 support?
306302
return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
307303

308304
case AMDGPU::OPERAND_REG_IMM_BF16:
309305
case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED:
310306
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
311-
case AMDGPU::OPERAND_REG_INLINE_AC_BF16:
312307
// We don't actually need to check Inv2Pi here because BF16 instructions can
313308
// only be emitted for targets that already support the feature.
314309
return getLitBF16Encoding(static_cast<uint16_t>(Imm));
315310

316311
case AMDGPU::OPERAND_REG_IMM_V2INT16:
317312
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
318-
case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
319313
return AMDGPU::getInlineEncodingV2I16(static_cast<uint32_t>(Imm))
320314
.value_or(255);
321315

322316
case AMDGPU::OPERAND_REG_IMM_V2FP16:
323317
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
324-
case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
325318
return AMDGPU::getInlineEncodingV2F16(static_cast<uint32_t>(Imm))
326319
.value_or(255);
327320

328321
case AMDGPU::OPERAND_REG_IMM_V2BF16:
329322
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
330-
case AMDGPU::OPERAND_REG_INLINE_AC_V2BF16:
331323
return AMDGPU::getInlineEncodingV2BF16(static_cast<uint32_t>(Imm))
332324
.value_or(255);
333325

‎llvm/lib/Target/AMDGPU/SIDefines.h

Lines changed: 3 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -224,8 +224,6 @@ enum OperandType : unsigned {
224224
OPERAND_REG_INLINE_C_V2INT16,
225225
OPERAND_REG_INLINE_C_V2BF16,
226226
OPERAND_REG_INLINE_C_V2FP16,
227-
OPERAND_REG_INLINE_C_V2INT32,
228-
OPERAND_REG_INLINE_C_V2FP32,
229227

230228
// Operand for split barrier inline constant
231229
OPERAND_INLINE_SPLIT_BARRIER_INT32,
@@ -235,17 +233,9 @@ enum OperandType : unsigned {
235233
OPERAND_KIMM16,
236234

237235
/// Operands with an AccVGPR register or inline constant
238-
OPERAND_REG_INLINE_AC_INT16,
239236
OPERAND_REG_INLINE_AC_INT32,
240-
OPERAND_REG_INLINE_AC_BF16,
241-
OPERAND_REG_INLINE_AC_FP16,
242237
OPERAND_REG_INLINE_AC_FP32,
243238
OPERAND_REG_INLINE_AC_FP64,
244-
OPERAND_REG_INLINE_AC_V2INT16,
245-
OPERAND_REG_INLINE_AC_V2BF16,
246-
OPERAND_REG_INLINE_AC_V2FP16,
247-
OPERAND_REG_INLINE_AC_V2INT32,
248-
OPERAND_REG_INLINE_AC_V2FP32,
249239

250240
// Operand for source modifiers for VOP instructions
251241
OPERAND_INPUT_MODS,
@@ -257,10 +247,10 @@ enum OperandType : unsigned {
257247
OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32,
258248

259249
OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
260-
OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32,
250+
OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_FP64,
261251

262-
OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16,
263-
OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32,
252+
OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT32,
253+
OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_FP64,
264254

265255
OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
266256
OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,

‎llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -439,8 +439,7 @@ bool SIFoldOperandsImpl::tryFoldImmWithOpSel(FoldCandidate &Fold) const {
439439
}
440440

441441
// This check is only useful for integer instructions
442-
if (OpType == AMDGPU::OPERAND_REG_IMM_V2INT16 ||
443-
OpType == AMDGPU::OPERAND_REG_INLINE_AC_V2INT16) {
442+
if (OpType == AMDGPU::OPERAND_REG_IMM_V2INT16) {
444443
if (AMDGPU::isInlinableLiteralV216(Lo << 16, OpType)) {
445444
Mod.setImm(NewModVal | SISrcMods::OP_SEL_0 | SISrcMods::OP_SEL_1);
446445
Old.ChangeToImmediate(static_cast<uint32_t>(Lo) << 16);

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -4380,9 +4380,7 @@ bool SIInstrInfo::isInlineConstant(int64_t Imm, uint8_t OperandType) const {
43804380
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
43814381
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
43824382
case AMDGPU::OPERAND_REG_IMM_V2FP32:
4383-
case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
43844383
case AMDGPU::OPERAND_REG_IMM_V2INT32:
4385-
case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
43864384
case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
43874385
case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
43884386
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32: {
@@ -4397,7 +4395,6 @@ bool SIInstrInfo::isInlineConstant(int64_t Imm, uint8_t OperandType) const {
43974395
return AMDGPU::isInlinableLiteral64(Imm, ST.hasInv2PiInlineImm());
43984396
case AMDGPU::OPERAND_REG_IMM_INT16:
43994397
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
4400-
case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
44014398
// We would expect inline immediates to not be concerned with an integer/fp
44024399
// distinction. However, in the case of 16-bit integer operations, the
44034400
// "floating point" values appear to not work. It seems read the low 16-bits
@@ -4411,20 +4408,16 @@ bool SIInstrInfo::isInlineConstant(int64_t Imm, uint8_t OperandType) const {
44114408
return AMDGPU::isInlinableIntLiteral(Imm);
44124409
case AMDGPU::OPERAND_REG_IMM_V2INT16:
44134410
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
4414-
case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
44154411
return AMDGPU::isInlinableLiteralV2I16(Imm);
44164412
case AMDGPU::OPERAND_REG_IMM_V2FP16:
44174413
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
4418-
case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
44194414
return AMDGPU::isInlinableLiteralV2F16(Imm);
44204415
case AMDGPU::OPERAND_REG_IMM_V2BF16:
44214416
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
4422-
case AMDGPU::OPERAND_REG_INLINE_AC_V2BF16:
44234417
return AMDGPU::isInlinableLiteralV2BF16(Imm);
44244418
case AMDGPU::OPERAND_REG_IMM_FP16:
44254419
case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
4426-
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
4427-
case AMDGPU::OPERAND_REG_INLINE_AC_FP16: {
4420+
case AMDGPU::OPERAND_REG_INLINE_C_FP16: {
44284421
if (isInt<16>(Imm) || isUInt<16>(Imm)) {
44294422
// A few special case instructions have 16-bit operands on subtargets
44304423
// where 16-bit instructions are not legal.
@@ -4439,8 +4432,7 @@ bool SIInstrInfo::isInlineConstant(int64_t Imm, uint8_t OperandType) const {
44394432
}
44404433
case AMDGPU::OPERAND_REG_IMM_BF16:
44414434
case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED:
4442-
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
4443-
case AMDGPU::OPERAND_REG_INLINE_AC_BF16: {
4435+
case AMDGPU::OPERAND_REG_INLINE_C_BF16: {
44444436
if (isInt<16>(Imm) || isUInt<16>(Imm)) {
44454437
int16_t Trunc = static_cast<int16_t>(Imm);
44464438
return ST.has16BitInsts() &&
@@ -4861,8 +4853,6 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
48614853
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
48624854
case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
48634855
case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
4864-
case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
4865-
case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
48664856
case AMDGPU::OPERAND_REG_INLINE_AC_FP64: {
48674857
if (!MO.isReg() && (!MO.isImm() || !isInlineConstant(MI, i))) {
48684858
ErrInfo = "Illegal immediate value for operand.";

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