Skip to content

Commit c2b4444

Browse files
committed
[RISCV][NFC] Combine redundant 'if' statements
Due to the repetitive occurrence of two consecutive simple "if" statements in the code, they can be merged together. Additionally, there is a single simple "switch-case" statement, but since there are only a few cases, it can be replaced with an "if" statement.
1 parent fde1ecd commit c2b4444

File tree

1 file changed

+6
-20
lines changed

1 file changed

+6
-20
lines changed

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 6 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -196,10 +196,7 @@ static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo,
196196
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
197197
uint64_t Address,
198198
const MCDisassembler *Decoder) {
199-
if (RegNo >= 32)
200-
return MCDisassembler::Fail;
201-
202-
if (RegNo % 2)
199+
if (RegNo >= 32 || RegNo % 2)
203200
return MCDisassembler::Fail;
204201

205202
const RISCVDisassembler *Dis =
@@ -216,10 +213,7 @@ static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
216213
static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
217214
uint64_t Address,
218215
const MCDisassembler *Decoder) {
219-
if (RegNo >= 32)
220-
return MCDisassembler::Fail;
221-
222-
if (RegNo % 4)
216+
if (RegNo >= 32 || RegNo % 4)
223217
return MCDisassembler::Fail;
224218

225219
const RISCVDisassembler *Dis =
@@ -236,10 +230,7 @@ static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
236230
static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo,
237231
uint64_t Address,
238232
const MCDisassembler *Decoder) {
239-
if (RegNo >= 32)
240-
return MCDisassembler::Fail;
241-
242-
if (RegNo % 8)
233+
if (RegNo >= 32 || RegNo % 8)
243234
return MCDisassembler::Fail;
244235

245236
const RISCVDisassembler *Dis =
@@ -256,16 +247,11 @@ static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo,
256247
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo,
257248
uint64_t Address,
258249
const MCDisassembler *Decoder) {
259-
MCRegister Reg = RISCV::NoRegister;
260-
switch (RegNo) {
261-
default:
250+
if (RegNo > 2) {
262251
return MCDisassembler::Fail;
263-
case 0:
264-
Reg = RISCV::V0;
265-
break;
266-
case 1:
267-
break;
268252
}
253+
MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister;
254+
269255
Inst.addOperand(MCOperand::createReg(Reg));
270256
return MCDisassembler::Success;
271257
}

0 commit comments

Comments
 (0)