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michaelmaitlandmichaelmaitland
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!fixup regbankselect G_IMPLICIT_DEF
1 parent 79eb8b6 commit c2cafff

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4 files changed

+137
-8
lines changed

4 files changed

+137
-8
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Lines changed: 26 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -207,6 +207,14 @@ bool RISCVRegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,
207207
return hasFPConstraints(MI, MRI, TRI);
208208
}
209209

210+
bool RISCVRegisterBankInfo::anyUseOnlyUseFP(
211+
Register Def, const MachineRegisterInfo &MRI,
212+
const TargetRegisterInfo &TRI) const {
213+
return any_of(
214+
MRI.use_nodbg_instructions(Def),
215+
[&](const MachineInstr &UseMI) { return onlyUsesFP(UseMI, MRI, TRI); });
216+
}
217+
210218
const RegisterBankInfo::InstructionMapping &
211219
RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
212220
const unsigned Opc = MI.getOpcode();
@@ -277,6 +285,19 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
277285
getFPValueMapping(Ty.getSizeInBits()),
278286
NumOperands);
279287
}
288+
case TargetOpcode::G_IMPLICIT_DEF: {
289+
Register Dst = MI.getOperand(0).getReg();
290+
auto Mapping = GPRValueMapping;
291+
// FIXME: May need to do a better job determining when to use FPRB.
292+
// For example, the look through COPY case:
293+
// %0:_(s32) = G_IMPLICIT_DEF
294+
// %1:_(s32) = COPY %0
295+
// $f10_d = COPY %1(s32)
296+
if (anyUseOnlyUseFP(Dst, MRI, TRI))
297+
Mapping = getFPValueMapping(MRI.getType(Dst).getSizeInBits());
298+
return getInstructionMapping(DefaultMappingID, /*Cost=*/1, Mapping,
299+
NumOperands);
300+
}
280301
}
281302

282303
SmallVector<const ValueMapping *, 4> OpdsMapping(NumOperands);
@@ -296,14 +317,11 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
296317
// Check if that load feeds fp instructions.
297318
// In that case, we want the default mapping to be on FPR
298319
// instead of blind map every scalar to GPR.
299-
if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
300-
[&](const MachineInstr &UseMI) {
301-
// If we have at least one direct use in a FP instruction,
302-
// assume this was a floating point load in the IR. If it was
303-
// not, we would have had a bitcast before reaching that
304-
// instruction.
305-
return onlyUsesFP(UseMI, MRI, TRI);
306-
}))
320+
if (anyUseOnlyUseFP(MI.getOperand(0).getReg(), MRI, TRI))
321+
// If we have at least one direct use in a FP instruction,
322+
// assume this was a floating point load in the IR. If it was
323+
// not, we would have had a bitcast before reaching that
324+
// instruction.
307325
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
308326

309327
break;

‎llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,10 @@ class RISCVRegisterBankInfo final : public RISCVGenRegisterBankInfo {
4848
bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
4949
const TargetRegisterInfo &TRI) const;
5050

51+
/// \returns true if any use of \p Def only user FPRs.
52+
bool anyUseOnlyUseFP(Register Def, const MachineRegisterInfo &MRI,
53+
const TargetRegisterInfo &TRI) const;
54+
5155
/// \returns true if \p MI only defines FPRs.
5256
bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
5357
const TargetRegisterInfo &TRI) const;

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv32 -mattr=+f -run-pass=regbankselect -simplify-mir -verify-machineinstrs %s -o - \
3+
# RUN: | FileCheck -check-prefix=RV32F %s
4+
5+
---
6+
name: implicit_def_gpr
7+
legalized: true
8+
body: |
9+
bb.0:
10+
; RV32F-LABEL: name: implicit_def_gpr
11+
; RV32F: [[DEF:%[0-9]+]]:gprb(s32) = G_IMPLICIT_DEF
12+
; RV32F-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[DEF]], [[DEF]]
13+
; RV32F-NEXT: $x10 = COPY [[ADD]](s32)
14+
%0:_(s32) = G_IMPLICIT_DEF
15+
%1:_(s32) = G_ADD %0, %0
16+
$x10 = COPY %1(s32)
17+
...
18+
---
19+
name: implicit_def_copy_gpr
20+
legalized: true
21+
body: |
22+
bb.0:
23+
; RV32F-LABEL: name: implicit_def_copy_gpr
24+
; RV32F: [[DEF:%[0-9]+]]:gprb(s32) = G_IMPLICIT_DEF
25+
; RV32F-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY [[DEF]](s32)
26+
; RV32F-NEXT: $x10 = COPY [[COPY]](s32)
27+
%0:_(s32) = G_IMPLICIT_DEF
28+
%1:_(s32) = COPY %0(s32)
29+
$x10 = COPY %1(s32)
30+
...
31+
32+
---
33+
name: implicit_def_fpr
34+
legalized: true
35+
body: |
36+
bb.0:
37+
; RV32F-LABEL: name: implicit_def_fpr
38+
; RV32F: [[DEF:%[0-9]+]]:fprb(s32) = G_IMPLICIT_DEF
39+
; RV32F-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[DEF]], [[DEF]]
40+
; RV32F-NEXT: $f10_f = COPY [[FADD]](s32)
41+
%0:_(s32) = G_IMPLICIT_DEF
42+
%1:_(s32) = G_FADD %0, %0
43+
$f10_f = COPY %1(s32)
44+
...
45+
---
46+
name: implicit_def_copy_fpr
47+
legalized: true
48+
body: |
49+
bb.0:
50+
; RV32F-LABEL: name: implicit_def_copy_fpr
51+
; RV32F: [[DEF:%[0-9]+]]:fprb(s32) = G_IMPLICIT_DEF
52+
; RV32F-NEXT: $f10_f = COPY [[DEF]](s32)
53+
%0:_(s32) = G_IMPLICIT_DEF
54+
$f10_f = COPY %0(s32)
55+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect -simplify-mir -verify-machineinstrs %s -o - \
3+
# RUN: | FileCheck -check-prefix=RV64D %s
4+
5+
---
6+
name: implicit_def_gpr
7+
legalized: true
8+
body: |
9+
bb.0:
10+
; RV64D-LABEL: name: implicit_def_gpr
11+
; RV64D: [[DEF:%[0-9]+]]:gprb(s64) = G_IMPLICIT_DEF
12+
; RV64D-NEXT: [[ADD:%[0-9]+]]:gprb(s64) = G_ADD [[DEF]], [[DEF]]
13+
; RV64D-NEXT: $x10 = COPY [[ADD]](s64)
14+
%0:_(s64) = G_IMPLICIT_DEF
15+
%1:_(s64) = G_ADD %0, %0
16+
$x10 = COPY %1(s64)
17+
...
18+
---
19+
name: implicit_def_copy_gpr
20+
legalized: true
21+
body: |
22+
bb.0:
23+
; RV64D-LABEL: name: implicit_def_copy_gpr
24+
; RV64D: [[DEF:%[0-9]+]]:gprb(s64) = G_IMPLICIT_DEF
25+
; RV64D-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY [[DEF]](s64)
26+
; RV64D-NEXT: $x10 = COPY [[COPY]](s64)
27+
%0:_(s64) = G_IMPLICIT_DEF
28+
%1:_(s64) = COPY %0(s64)
29+
$x10 = COPY %1(s64)
30+
...
31+
32+
---
33+
name: implicit_def_fpr
34+
legalized: true
35+
body: |
36+
bb.0:
37+
; RV64D-LABEL: name: implicit_def_fpr
38+
; RV64D: [[DEF:%[0-9]+]]:fprb(s64) = G_IMPLICIT_DEF
39+
; RV64D-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[DEF]], [[DEF]]
40+
; RV64D-NEXT: $f10_d = COPY [[FADD]](s64)
41+
%0:_(s64) = G_IMPLICIT_DEF
42+
%1:_(s64) = G_FADD %0, %0
43+
$f10_d = COPY %1(s64)
44+
...
45+
---
46+
name: implicit_def_copy_fpr
47+
legalized: true
48+
body: |
49+
bb.0:
50+
%0:_(s64) = G_IMPLICIT_DEF
51+
$f10_d = COPY %0(s64)
52+
...

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