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Clang: Define macro _MIPS_SPFPSET
GCC defines this macro for how many single-precision floating point registers can be used. If the -mno-odd-spreg option is given, it will be 16; if either -mno-odd-spreg nor -modd-spreg are given, we set it to 16 for FPXX. Reviewed By: theraven Differential Revision: https://reviews.llvm.org/D157896
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‎clang/lib/Basic/Targets/Mips.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -149,6 +149,10 @@ void MipsTargetInfo::getTargetDefines(const LangOptions &Opts,
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Builder.defineMacro("_MIPS_FPSET", Twine(32));
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else
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Builder.defineMacro("_MIPS_FPSET", Twine(16));
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if (NoOddSpreg)
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Builder.defineMacro("_MIPS_SPFPSET", Twine(16));
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else
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Builder.defineMacro("_MIPS_SPFPSET", Twine(32));
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if (IsMips16)
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Builder.defineMacro("__mips16", Twine(1));

‎clang/lib/Basic/Targets/Mips.h

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,7 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
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bool HasMSA;
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bool DisableMadd4;
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bool UseIndirectJumpHazard;
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bool NoOddSpreg;
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protected:
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enum FPModeEnum { FPXX, FP32, FP64 } FPMode;
@@ -313,6 +314,8 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
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FloatABI = HardFloat;
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DspRev = NoDSP;
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FPMode = isFP64Default() ? FP64 : FPXX;
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NoOddSpreg = false;
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bool OddSpregGiven = false;
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for (const auto &Feature : Features) {
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if (Feature == "+single-float")
@@ -349,8 +352,18 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
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IsNoABICalls = true;
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else if (Feature == "+use-indirect-jump-hazard")
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UseIndirectJumpHazard = true;
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else if (Feature == "+nooddspreg") {
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NoOddSpreg = true;
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OddSpregGiven = false;
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} else if (Feature == "-nooddspreg") {
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NoOddSpreg = false;
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OddSpregGiven = true;
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}
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}
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if (FPMode == FPXX && !OddSpregGiven)
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NoOddSpreg = true;
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setDataLayout();
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return true;

‎clang/test/Preprocessor/init-mips.c

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
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// MIPS32BE:#define _MIPS_ARCH_MIPS32R2 1
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// MIPS32BE:#define _MIPS_FPSET 16
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// MIPS32BE:#define _MIPS_SIM _ABIO32
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// MIPS32BE:#define _MIPS_SPFPSET 16
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// MIPS32BE:#define _MIPS_SZINT 32
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// MIPS32BE:#define _MIPS_SZLONG 32
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// MIPS32BE:#define _MIPS_SZPTR 32
@@ -220,6 +221,7 @@
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// MIPS32EL:#define _MIPS_ARCH_MIPS32R2 1
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// MIPS32EL:#define _MIPS_FPSET 16
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// MIPS32EL:#define _MIPS_SIM _ABIO32
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// MIPS32EL:#define _MIPS_SPFPSET 16
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// MIPS32EL:#define _MIPS_SZINT 32
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// MIPS32EL:#define _MIPS_SZLONG 32
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// MIPS32EL:#define _MIPS_SZPTR 32
@@ -432,6 +434,7 @@
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// MIPSN32BE: #define _MIPS_FPSET 32
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// MIPSN32BE: #define _MIPS_ISA _MIPS_ISA_MIPS64
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// MIPSN32BE: #define _MIPS_SIM _ABIN32
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// MIPSN32BE: #define _MIPS_SPFPSET 32
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// MIPSN32BE: #define _MIPS_SZINT 32
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// MIPSN32BE: #define _MIPS_SZLONG 32
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// MIPSN32BE: #define _MIPS_SZPTR 32
@@ -739,6 +742,7 @@
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// MIPSN32EL: #define _MIPS_FPSET 32
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// MIPSN32EL: #define _MIPS_ISA _MIPS_ISA_MIPS64
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// MIPSN32EL: #define _MIPS_SIM _ABIN32
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// MIPSN32EL: #define _MIPS_SPFPSET 32
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// MIPSN32EL: #define _MIPS_SZINT 32
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// MIPSN32EL: #define _MIPS_SZLONG 32
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// MIPSN32EL: #define _MIPS_SZPTR 32
@@ -1043,6 +1047,7 @@
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// MIPS64BE:#define _MIPS_ARCH_MIPS64R2 1
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// MIPS64BE:#define _MIPS_FPSET 32
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// MIPS64BE:#define _MIPS_SIM _ABI64
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// MIPS64BE:#define _MIPS_SPFPSET 32
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// MIPS64BE:#define _MIPS_SZINT 32
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// MIPS64BE:#define _MIPS_SZLONG 64
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// MIPS64BE:#define _MIPS_SZPTR 64
@@ -1253,6 +1258,7 @@
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// MIPS64EL:#define _MIPS_ARCH_MIPS64R2 1
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// MIPS64EL:#define _MIPS_FPSET 32
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// MIPS64EL:#define _MIPS_SIM _ABI64
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// MIPS64EL:#define _MIPS_SPFPSET 32
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// MIPS64EL:#define _MIPS_SZINT 32
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// MIPS64EL:#define _MIPS_SZLONG 64
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// MIPS64EL:#define _MIPS_SZPTR 64
@@ -1506,6 +1512,7 @@
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// MIPS-ARCH-32R6:#define _MIPS_ARCH "mips32r6"
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// MIPS-ARCH-32R6:#define _MIPS_ARCH_MIPS32R6 1
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// MIPS-ARCH-32R6:#define _MIPS_ISA _MIPS_ISA_MIPS32
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// MIPS-ARCH-32R6:#define __mips_fpr 64
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// MIPS-ARCH-32R6:#define __mips_isa_rev 6
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// RUN: %clang_cc1 -E -dM -ffreestanding -triple=mips64-none-none \
@@ -1682,14 +1689,28 @@
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// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-NOFP %s
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// MIPS32-NOFP:#define __mips_fpr 0
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// RUN: %clang_cc1 -target-feature -nooddspreg \
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// RUN: -E -dM -triple=mips-none-none < /dev/null \
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// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-NOFP-ODD %s
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// MIPS32-NOFP-ODD:#define _MIPS_SPFPSET 32
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// MIPS32-NOFP-ODD:#define __mips_fpr 0
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// RUN: %clang_cc1 -target-feature +nooddspreg -target-feature -fp64 \
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// RUN: -E -dM -triple=mips-none-none < /dev/null \
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// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-FP64-NOODD %s
1701+
// MIPS32-FP64-NOODD:#define _MIPS_SPFPSET 16
1702+
// MIPS32-FP64-NOODD:#define __mips_fpr 32
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// RUN: %clang_cc1 -target-feature +fpxx \
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// RUN: -E -dM -triple=mips-none-none < /dev/null \
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// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFPXX %s
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// MIPS32-MFPXX:#define _MIPS_SPFPSET 16
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// MIPS32-MFPXX:#define __mips_fpr 0
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// RUN: %clang_cc1 -target-cpu mips32r6 -target-feature +fpxx \
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// RUN: -E -dM -triple=mips-none-none < /dev/null \
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// RUN: | FileCheck -match-full-lines -check-prefix MIPS32R6-MFPXX %s
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// MIPS32R6-MFPXX:#define _MIPS_SPFPSET 16
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// MIPS32R6-MFPXX:#define __mips_fpr 0
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// RUN: %clang_cc1 \
@@ -1716,30 +1737,35 @@
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// RUN: -E -dM -triple=mips-none-none < /dev/null \
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// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFP32 %s
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// MIPS32-MFP32:#define _MIPS_FPSET 16
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// MIPS32-MFP32:#define _MIPS_SPFPSET 32
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// MIPS32-MFP32:#define __mips_fpr 32
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17211743
// RUN: %clang_cc1 -target-feature +fp64 \
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// RUN: -E -dM -triple=mips-none-none < /dev/null \
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// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFP64 %s
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// MIPS32-MFP64:#define _MIPS_FPSET 32
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// MIPS32-MFP64:#define _MIPS_SPFPSET 32
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// MIPS32-MFP64:#define __mips_fpr 64
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//
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// RUN: %clang_cc1 -target-feature +single-float \
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// RUN: -E -dM -triple=mips-none-none < /dev/null \
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// RUN: | FileCheck -match-full-lines -check-prefix MIPS32-MFP32SF %s
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// MIPS32-MFP32SF:#define _MIPS_FPSET 32
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// MIPS32-MFP32SF:#define _MIPS_SPFPSET 16
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// MIPS32-MFP32SF:#define __mips_fpr 0
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17331757
// RUN: %clang_cc1 -target-feature +fp64 \
17341758
// RUN: -E -dM -triple=mips64-none-none < /dev/null \
17351759
// RUN: | FileCheck -match-full-lines -check-prefix MIPS64-MFP64 %s
17361760
// MIPS64-MFP64:#define _MIPS_FPSET 32
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// MIPS64-MFP64:#define _MIPS_SPFPSET 32
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// MIPS64-MFP64:#define __mips_fpr 64
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// RUN: %clang_cc1 -target-feature -fp64 -target-feature +single-float \
17401765
// RUN: -E -dM -triple=mips64-none-none < /dev/null \
17411766
// RUN: | FileCheck -match-full-lines -check-prefix MIPS64-NOMFP64 %s
17421767
// MIPS64-NOMFP64:#define _MIPS_FPSET 32
1768+
// MIPS64-NOMFP64:#define _MIPS_SPFPSET 32
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// MIPS64-NOMFP64:#define __mips_fpr 32
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17451771
// RUN: %clang_cc1 -target-cpu mips32r6 \
@@ -1749,6 +1775,7 @@
17491775
// RUN: -E -dM -triple=mips64-none-none < /dev/null \
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// RUN: | FileCheck -match-full-lines -check-prefix MIPS-XXR6 %s
17511777
// MIPS-XXR6:#define _MIPS_FPSET 32
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// MIPS-XXR6:#define _MIPS_SPFPSET 32
17521779
// MIPS-XXR6:#define __mips_fpr 64
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// MIPS-XXR6:#define __mips_nan2008 1
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