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[AArch64][GlobalISel] Fix not extending GPR32->GPR64 result of anyext indexed load.
Was causing assertions to fail.
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3 files changed

+49
-5
lines changed

3 files changed

+49
-5
lines changed

llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -114,6 +114,21 @@ class GIndexedExtLoad : public GIndexedLoad {
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}
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};
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/// Represents either G_INDEXED_LOAD, G_INDEXED_ZEXTLOAD or G_INDEXED_SEXTLOAD.
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class GIndexedAnyExtLoad : public GIndexedLoad {
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public:
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static bool classof(const MachineInstr *MI) {
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switch (MI->getOpcode()) {
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case TargetOpcode::G_INDEXED_LOAD:
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case TargetOpcode::G_INDEXED_ZEXTLOAD:
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case TargetOpcode::G_INDEXED_SEXTLOAD:
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return true;
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default:
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return false;
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}
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}
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};
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/// Represents a G_ZEXTLOAD.
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class GIndexedZExtLoad : GIndexedExtLoad {
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public:

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -5610,7 +5610,7 @@ MachineInstr *AArch64InstructionSelector::tryAdvSIMDModImmFP(
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bool AArch64InstructionSelector::selectIndexedExtLoad(
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MachineInstr &MI, MachineRegisterInfo &MRI) {
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auto &ExtLd = cast<GIndexedExtLoad>(MI);
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auto &ExtLd = cast<GIndexedAnyExtLoad>(MI);
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Register Dst = ExtLd.getDstReg();
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Register WriteBack = ExtLd.getWritebackReg();
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Register Base = ExtLd.getBaseReg();
@@ -5697,10 +5697,6 @@ bool AArch64InstructionSelector::selectIndexedExtLoad(
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bool AArch64InstructionSelector::selectIndexedLoad(MachineInstr &MI,
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MachineRegisterInfo &MRI) {
5700-
// TODO: extending loads.
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if (isa<GIndexedExtLoad>(MI))
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return false;
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auto &Ld = cast<GIndexedLoad>(MI);
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Register Dst = Ld.getDstReg();
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Register WriteBack = Ld.getWritebackReg();
@@ -5710,6 +5706,9 @@ bool AArch64InstructionSelector::selectIndexedLoad(MachineInstr &MI,
57105706
"Unexpected type for indexed load");
57115707
unsigned MemSize = Ld.getMMO().getMemoryType().getSizeInBytes();
57125708

5709+
if (MemSize < MRI.getType(Dst).getSizeInBytes())
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return selectIndexedExtLoad(MI, MRI);
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57135712
unsigned Opc = 0;
57145713
if (Ld.isPre()) {
57155714
static constexpr unsigned GPROpcodes[] = {
Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -global-isel %s -o - | FileCheck %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-macosx14.0.0"
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define void @test() {
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; CHECK-LABEL: test:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset w30, -8
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: mov x1, xzr
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; CHECK-NEXT: ldr x8, [x0]
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; CHECK-NEXT: ldr w9, [x8], #8
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; CHECK-NEXT: str x8, [x0]
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; CHECK-NEXT: str x9, [sp]
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; CHECK-NEXT: bl _sprintf
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; CHECK-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: ret
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entry:
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%0 = va_arg ptr null, i32
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%sprintf1776 = tail call i32 (ptr, ptr, ...) @sprintf(ptr null, ptr null, i32 %0)
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ret void
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}
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declare i32 @sprintf(ptr, ptr, ...)

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