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More tests which can use the FORM_TRANSPOSED pseudo nodes
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7 files changed

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-254
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‎llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll

Lines changed: 137 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,11 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2-
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2,+fp8 -verify-machineinstrs -force-streaming < %s | FileCheck %s
2+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2,+fp8 -verify-machineinstrs -force-streaming -enable-subreg-liveness < %s | FileCheck %s
33

44
; FCVT / FCVTN / BFCVT
55

66
define <vscale x 16 x i8> @fcvt_x2(<vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1) {
77
; CHECK-LABEL: fcvt_x2:
88
; CHECK: // %bb.0:
9-
; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
10-
; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
119
; CHECK-NEXT: fcvt z0.b, { z0.h, z1.h }
1210
; CHECK-NEXT: ret
1311
%res = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(<vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1)
@@ -17,24 +15,114 @@ define <vscale x 16 x i8> @fcvt_x2(<vscale x 8 x half> %zn0, <vscale x 8 x half>
1715
define <vscale x 16 x i8> @fcvt_x4(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3) {
1816
; CHECK-LABEL: fcvt_x4:
1917
; CHECK: // %bb.0:
20-
; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
21-
; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
22-
; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
23-
; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
2418
; CHECK-NEXT: fcvt z0.b, { z0.s - z3.s }
2519
; CHECK-NEXT: ret
2620
%res = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1,
2721
<vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3)
2822
ret <vscale x 16 x i8> %res
2923
}
3024

25+
define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @fcvt_x4_tuple(i64 %stride, ptr %ptr) {
26+
; CHECK-LABEL: fcvt_x4_tuple:
27+
; CHECK: // %bb.0: // %entry
28+
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
29+
; CHECK-NEXT: addvl sp, sp, #-10
30+
; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Folded Spill
31+
; CHECK-NEXT: ptrue pn8.b
32+
; CHECK-NEXT: str z19, [sp, #1, mul vl] // 16-byte Folded Spill
33+
; CHECK-NEXT: st1b { z10.b, z11.b }, pn8, [sp, #6, mul vl] // 32-byte Folded Spill
34+
; CHECK-NEXT: str z18, [sp, #2, mul vl] // 16-byte Folded Spill
35+
; CHECK-NEXT: str z17, [sp, #3, mul vl] // 16-byte Folded Spill
36+
; CHECK-NEXT: str z16, [sp, #4, mul vl] // 16-byte Folded Spill
37+
; CHECK-NEXT: str z14, [sp, #5, mul vl] // 16-byte Folded Spill
38+
; CHECK-NEXT: st1b { z8.b, z9.b }, pn8, [sp, #8, mul vl] // 32-byte Folded Spill
39+
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xd0, 0x00, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 80 * VG
40+
; CHECK-NEXT: .cfi_offset w29, -16
41+
; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 16 - 8 * VG
42+
; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x70, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d9 @ cfa - 16 - 16 * VG
43+
; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x68, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d10 @ cfa - 16 - 24 * VG
44+
; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x60, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d11 @ cfa - 16 - 32 * VG
45+
; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x58, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d14 @ cfa - 16 - 40 * VG
46+
; CHECK-NEXT: ptrue pn8.b
47+
; CHECK-NEXT: lsl x9, x0, #1
48+
; CHECK-NEXT: add x8, x1, x0
49+
; CHECK-NEXT: ld1w { z0.s - z3.s }, pn8/z, [x1]
50+
; CHECK-NEXT: ld1w { z4.s - z7.s }, pn8/z, [x8]
51+
; CHECK-NEXT: add x10, x1, x9
52+
; CHECK-NEXT: add x8, x8, x9
53+
; CHECK-NEXT: mov z8.d, z2.d
54+
; CHECK-NEXT: ld1w { z2.s, z6.s, z10.s, z14.s }, pn8/z, [x10]
55+
; CHECK-NEXT: ld1w { z16.s - z19.s }, pn8/z, [x8]
56+
; CHECK-NEXT: mov z24.d, z0.d
57+
; CHECK-NEXT: mov z28.d, z1.d
58+
; CHECK-NEXT: mov z25.d, z4.d
59+
; CHECK-NEXT: mov z29.d, z5.d
60+
; CHECK-NEXT: mov z9.d, z5.d
61+
; CHECK-NEXT: ptrue pn8.b
62+
; CHECK-NEXT: mov z26.d, z2.d
63+
; CHECK-NEXT: mov z30.d, z6.d
64+
; CHECK-NEXT: mov z27.d, z16.d
65+
; CHECK-NEXT: mov z31.d, z17.d
66+
; CHECK-NEXT: mov z11.d, z18.d
67+
; CHECK-NEXT: mov z16.d, z3.d
68+
; CHECK-NEXT: mov z17.d, z7.d
69+
; CHECK-NEXT: mov z18.d, z14.d
70+
; CHECK-NEXT: fcvt z0.b, { z24.s - z27.s }
71+
; CHECK-NEXT: fcvt z1.b, { z28.s - z31.s }
72+
; CHECK-NEXT: fcvt z2.b, { z8.s - z11.s }
73+
; CHECK-NEXT: fcvt z3.b, { z16.s - z19.s }
74+
; CHECK-NEXT: ldr z19, [sp, #1, mul vl] // 16-byte Folded Reload
75+
; CHECK-NEXT: ldr z18, [sp, #2, mul vl] // 16-byte Folded Reload
76+
; CHECK-NEXT: ldr z17, [sp, #3, mul vl] // 16-byte Folded Reload
77+
; CHECK-NEXT: ldr z16, [sp, #4, mul vl] // 16-byte Folded Reload
78+
; CHECK-NEXT: ldr z14, [sp, #5, mul vl] // 16-byte Folded Reload
79+
; CHECK-NEXT: ld1b { z10.b, z11.b }, pn8/z, [sp, #6, mul vl] // 32-byte Folded Reload
80+
; CHECK-NEXT: ld1b { z8.b, z9.b }, pn8/z, [sp, #8, mul vl] // 32-byte Folded Reload
81+
; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Folded Reload
82+
; CHECK-NEXT: addvl sp, sp, #10
83+
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
84+
; CHECK-NEXT: ret
85+
entry:
86+
%0 = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8()
87+
%1 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %ptr)
88+
%2 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 0
89+
%3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 1
90+
%4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 2
91+
%5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 3
92+
%arrayidx2 = getelementptr inbounds i8, ptr %ptr, i64 %stride
93+
%6 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %arrayidx2)
94+
%7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 0
95+
%8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 1
96+
%9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 2
97+
%10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 3
98+
%mul3 = shl i64 %stride, 1
99+
%arrayidx4 = getelementptr inbounds i8, ptr %ptr, i64 %mul3
100+
%11 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %arrayidx4)
101+
%12 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 0
102+
%13 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 1
103+
%14 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 2
104+
%15 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 3
105+
%mul5 = mul i64 %stride, 3
106+
%arrayidx6 = getelementptr inbounds i8, ptr %ptr, i64 %mul5
107+
%16 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %arrayidx6)
108+
%17 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 0
109+
%18 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 1
110+
%19 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 2
111+
%20 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 3
112+
%res1 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float> %2, <vscale x 4 x float> %7, <vscale x 4 x float> %12, <vscale x 4 x float> %17)
113+
%res2 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float> %3, <vscale x 4 x float> %8, <vscale x 4 x float> %13, <vscale x 4 x float> %18)
114+
%res3 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float> %4, <vscale x 4 x float> %8, <vscale x 4 x float> %14, <vscale x 4 x float> %19)
115+
%res4 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float> %5, <vscale x 4 x float> %10, <vscale x 4 x float> %15, <vscale x 4 x float> %20)
116+
%ins1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %res1, 0
117+
%ins2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %ins1, <vscale x 16 x i8> %res2, 1
118+
%ins3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %ins2, <vscale x 16 x i8> %res3, 2
119+
%ins4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %ins3, <vscale x 16 x i8> %res4, 3
120+
ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %ins4
121+
}
122+
31123
define <vscale x 16 x i8> @fcvtn(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3) {
32124
; CHECK-LABEL: fcvtn:
33125
; CHECK: // %bb.0:
34-
; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
35-
; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
36-
; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
37-
; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3
38126
; CHECK-NEXT: fcvtn z0.b, { z0.s - z3.s }
39127
; CHECK-NEXT: ret
40128
%res = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.x4(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1,
@@ -45,14 +133,50 @@ define <vscale x 16 x i8> @fcvtn(<vscale x 4 x float> %zn0, <vscale x 4 x float>
45133
define <vscale x 16 x i8> @bfcvt(<vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1) {
46134
; CHECK-LABEL: bfcvt:
47135
; CHECK: // %bb.0:
48-
; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
49-
; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
50136
; CHECK-NEXT: bfcvt z0.b, { z0.h, z1.h }
51137
; CHECK-NEXT: ret
52138
%res = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1)
53139
ret <vscale x 16 x i8> %res
54140
}
55141

142+
143+
define { <vscale x 16 x i8>, <vscale x 16 x i8> } @bfcvt_tuple(i64 %stride, ptr %ptr) {
144+
; CHECK-LABEL: bfcvt_tuple:
145+
; CHECK: // %bb.0: // %entry
146+
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
147+
; CHECK-NEXT: addvl sp, sp, #-1
148+
; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Folded Spill
149+
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
150+
; CHECK-NEXT: .cfi_offset w29, -16
151+
; CHECK-NEXT: ptrue pn8.b
152+
; CHECK-NEXT: add x8, x1, x0
153+
; CHECK-NEXT: ld1h { z0.h, z1.h }, pn8/z, [x1]
154+
; CHECK-NEXT: ld1h { z2.h, z3.h }, pn8/z, [x8]
155+
; CHECK-NEXT: mov z4.d, z0.d
156+
; CHECK-NEXT: mov z5.d, z2.d
157+
; CHECK-NEXT: mov z2.d, z1.d
158+
; CHECK-NEXT: bfcvt z0.b, { z4.h, z5.h }
159+
; CHECK-NEXT: bfcvt z1.b, { z2.h, z3.h }
160+
; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Folded Reload
161+
; CHECK-NEXT: addvl sp, sp, #1
162+
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
163+
; CHECK-NEXT: ret
164+
entry:
165+
%0 = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8()
166+
%1 = tail call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld1.pn.x2.nxv8bf16(target("aarch64.svcount") %0, ptr %ptr)
167+
%2 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, 0
168+
%3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, 1
169+
%arrayidx2 = getelementptr inbounds i8, ptr %ptr, i64 %stride
170+
%4 = tail call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld1.pn.x2.nxv8bf16(target("aarch64.svcount") %0, ptr %arrayidx2)
171+
%5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
172+
%6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
173+
%res1 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %5)
174+
%res2 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %6)
175+
%ins1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %res1, 0
176+
%ins2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %ins1, <vscale x 16 x i8> %res2, 1
177+
ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %ins2
178+
}
179+
56180
; F1CVT / F2CVT
57181

58182
define { <vscale x 8 x half>, <vscale x 8 x half> } @f1cvt(<vscale x 16 x i8> %zm) {

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