We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 566152d commit c47a4b3Copy full SHA for c47a4b3
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -2212,7 +2212,8 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
2212
2213
switch (getTypeAction(InVT)) {
2214
case TargetLowering::TypePromoteInteger: {
2215
- if (OutVT.isVector()) {
+ // TODO: Handle big endian
2216
+ if (OutVT.isVector() && DAG.getDataLayout().isLittleEndian()) {
2217
EVT EltVT = OutVT.getVectorElementType();
2218
TypeSize EltSize = EltVT.getSizeInBits();
2219
TypeSize NInSize = NInVT.getSizeInBits();
0 commit comments