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[ValueTracking] Infer knownbits from fp classes
1 parent 763c410 commit c488c79

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6 files changed

+67
-57
lines changed

6 files changed

+67
-57
lines changed

‎llvm/include/llvm/Analysis/ValueTracking.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -263,6 +263,11 @@ struct KnownFPClass {
263263
return (KnownFPClasses & Mask) == fcNone;
264264
}
265265

266+
/// Return true if it's known this can only be one of the mask entries.
267+
bool isKnownOnly(FPClassTest Mask) const {
268+
return (KnownFPClasses & ~Mask) == fcNone;
269+
}
270+
266271
bool isUnknown() const {
267272
return KnownFPClasses == fcAllFlags && !SignBit;
268273
}

‎llvm/lib/Analysis/ValueTracking.cpp

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1108,6 +1108,40 @@ static void computeKnownBitsFromOperator(const Operator *I,
11081108
break;
11091109
}
11101110

1111+
Value *V;
1112+
// Handle bitcast from floating point to integer.
1113+
if (match(const_cast<Operator *>(I), m_ElementWiseBitCast(m_Value(V))) &&
1114+
V->getType()->isFPOrFPVectorTy()) {
1115+
KnownFPClass Result = computeKnownFPClass(V, fcAllFlags, Depth + 1, Q);
1116+
if (Result.SignBit) {
1117+
if (*Result.SignBit)
1118+
Known.makeNegative();
1119+
else
1120+
Known.makeNonNegative();
1121+
}
1122+
1123+
Type *FPType = V->getType()->getScalarType();
1124+
if (FPType->isIEEELikeFPTy()) {
1125+
int MantissaWidth = FPType->getFPMantissaWidth();
1126+
if (MantissaWidth != -1) {
1127+
if (Result.isKnownOnly(fcInf)) {
1128+
Known.Zero.setLowBits(MantissaWidth);
1129+
Known.One.setBits(MantissaWidth, BitWidth - 1);
1130+
} else if (Result.isKnownOnly(fcZero)) {
1131+
Known.Zero.setLowBits(BitWidth - 1);
1132+
} else if (Result.isKnownOnly(fcInf | fcNan)) {
1133+
Known.One.setBits(MantissaWidth, BitWidth - 1);
1134+
} else if (Result.isKnownOnly(fcSubnormal | fcZero)) {
1135+
Known.Zero.setBits(MantissaWidth, BitWidth - 1);
1136+
} else if (Result.isKnownOnly(fcInf | fcZero)) {
1137+
Known.Zero.setLowBits(MantissaWidth);
1138+
}
1139+
}
1140+
}
1141+
1142+
break;
1143+
}
1144+
11111145
// Handle cast from vector integer type to scalar or vector integer.
11121146
auto *SrcVecTy = dyn_cast<FixedVectorType>(SrcTy);
11131147
if (!SrcVecTy || !SrcVecTy->getElementType()->isIntegerTy() ||

‎llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2216,7 +2216,7 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp(float %x, i32 %y)
22162216
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
22172217
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
22182218
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32
2219-
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[__POW_SIGN]], [[TMP3]]
2219+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]]
22202220
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
22212221
; CHECK-NEXT: ret float [[TMP5]]
22222222
;
@@ -2304,7 +2304,7 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp(float %x, i32 %y)
23042304
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
23052305
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
23062306
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32
2307-
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[__POW_SIGN]], [[TMP3]]
2307+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]]
23082308
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
23092309
; CHECK-NEXT: ret float [[TMP5]]
23102310
;
@@ -2353,7 +2353,7 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp_i256(float %x, i2
23532353
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
23542354
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
23552355
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32
2356-
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[__POW_SIGN]], [[TMP3]]
2356+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]]
23572357
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
23582358
; CHECK-NEXT: ret float [[TMP5]]
23592359
;
@@ -2376,7 +2376,7 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp_i256(float %x, i2
23762376
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
23772377
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
23782378
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32
2379-
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[__POW_SIGN]], [[TMP3]]
2379+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]]
23802380
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
23812381
; CHECK-NEXT: ret float [[TMP5]]
23822382
;
@@ -2399,7 +2399,7 @@ define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_sitofp(<2 x floa
23992399
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>
24002400
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP2]]
24012401
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[__EXP2]] to <2 x i32>
2402-
; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[__POW_SIGN]], [[TMP3]]
2402+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint <2 x i32> [[__POW_SIGN]], [[TMP3]]
24032403
; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to <2 x float>
24042404
; CHECK-NEXT: ret <2 x float> [[TMP5]]
24052405
;
@@ -2448,7 +2448,7 @@ define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_uitofp(<2 x floa
24482448
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>
24492449
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP2]]
24502450
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[__EXP2]] to <2 x i32>
2451-
; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[__POW_SIGN]], [[TMP3]]
2451+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint <2 x i32> [[__POW_SIGN]], [[TMP3]]
24522452
; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to <2 x float>
24532453
; CHECK-NEXT: ret <2 x float> [[TMP5]]
24542454
;
@@ -2560,7 +2560,7 @@ define float @test_pow_afn_f32_nnan_ninf__y_known_integral_trunc(float %x, float
25602560
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
25612561
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
25622562
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32
2563-
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[__POW_SIGN]], [[TMP3]]
2563+
; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]]
25642564
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
25652565
; CHECK-NEXT: ret float [[TMP5]]
25662566
;

‎llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -680,7 +680,7 @@ define float @test_pown_afn_nnan_ninf_f32(float %x, i32 %y) {
680680
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32
681681
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]]
682682
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32
683-
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]]
683+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]]
684684
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
685685
; CHECK-NEXT: ret float [[TMP3]]
686686
;
@@ -703,7 +703,7 @@ define <2 x float> @test_pown_afn_nnan_ninf_v2f32(<2 x float> %x, <2 x i32> %y)
703703
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>
704704
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP0]]
705705
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[__EXP2]] to <2 x i32>
706-
; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[__POW_SIGN]], [[TMP1]]
706+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint <2 x i32> [[__POW_SIGN]], [[TMP1]]
707707
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float>
708708
; CHECK-NEXT: ret <2 x float> [[TMP3]]
709709
;
@@ -772,7 +772,7 @@ define half @test_pown_afn_nnan_ninf_f16(half %x, i32 %y) {
772772
; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[X]] to i16
773773
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i16 [[__YEVEN]], [[TMP0]]
774774
; CHECK-NEXT: [[TMP1:%.*]] = bitcast half [[__EXP2]] to i16
775-
; CHECK-NEXT: [[TMP2:%.*]] = or i16 [[__POW_SIGN]], [[TMP1]]
775+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i16 [[__POW_SIGN]], [[TMP1]]
776776
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i16 [[TMP2]] to half
777777
; CHECK-NEXT: ret half [[TMP3]]
778778
;
@@ -795,7 +795,7 @@ define <2 x half> @test_pown_afn_nnan_ninf_v2f16(<2 x half> %x, <2 x i32> %y) {
795795
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x half> [[X]] to <2 x i16>
796796
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i16> [[__YEVEN]], [[TMP0]]
797797
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x half> [[__EXP2]] to <2 x i16>
798-
; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i16> [[__POW_SIGN]], [[TMP1]]
798+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint <2 x i16> [[__POW_SIGN]], [[TMP1]]
799799
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to <2 x half>
800800
; CHECK-NEXT: ret <2 x half> [[TMP3]]
801801
;
@@ -829,7 +829,7 @@ define float @test_pown_fast_f32_strictfp(float %x, i32 %y) #1 {
829829
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32
830830
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]]
831831
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32
832-
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]]
832+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]]
833833
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
834834
; CHECK-NEXT: ret float [[TMP3]]
835835
;
@@ -1075,7 +1075,7 @@ define float @test_pown_afn_ninf_nnan_f32__x_known_positive(float nofpclass(ninf
10751075
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32
10761076
; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]]
10771077
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32
1078-
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]]
1078+
; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]]
10791079
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
10801080
; CHECK-NEXT: ret float [[TMP3]]
10811081
;

‎llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -360,7 +360,7 @@ declare half @_Z4pownDhi(half, i32)
360360
; GCN-NATIVE: %0 = bitcast half %x to i16
361361
; GCN-NATIVE: %__pow_sign = and i16 %__yeven, %0
362362
; GCN-NATIVE: %1 = bitcast half %__exp2 to i16
363-
; GCN-NATIVE: %2 = or i16 %__pow_sign, %1
363+
; GCN-NATIVE: %2 = or disjoint i16 %__pow_sign, %1
364364
; GCN-NATIVE: %3 = bitcast i16 %2 to half
365365
define half @test_pown_f16(half %x, i32 %y) {
366366
entry:
@@ -378,7 +378,7 @@ declare float @_Z4pownfi(float, i32)
378378
; GCN: %[[r0:.*]] = bitcast float %tmp to i32
379379
; GCN: %__pow_sign = and i32 %[[r0]], -2147483648
380380
; GCN: %[[r1:.*]] = bitcast float %__exp2 to i32
381-
; GCN: %[[r2:.*]] = or i32 %__pow_sign, %[[r1]]
381+
; GCN: %[[r2:.*]] = or disjoint i32 %__pow_sign, %[[r1]]
382382
; GCN: store i32 %[[r2]], ptr addrspace(1) %a, align 4
383383
define amdgpu_kernel void @test_pow(ptr addrspace(1) nocapture %a) {
384384
entry:
@@ -414,7 +414,7 @@ entry:
414414
; GCN: %[[r0:.*]] = bitcast float %tmp to i32
415415
; GCN: %__pow_sign = and i32 %__yeven, %[[r0]]
416416
; GCN: %[[r1:.*]] = bitcast float %__exp2 to i32
417-
; GCN: %[[r2:.*]] = or i32 %__pow_sign, %[[r1]]
417+
; GCN: %[[r2:.*]] = or disjoint i32 %__pow_sign, %[[r1]]
418418
; GCN: store i32 %[[r2]], ptr addrspace(1) %a, align 4
419419
define amdgpu_kernel void @test_pown(ptr addrspace(1) nocapture %a) {
420420
entry:
@@ -438,7 +438,7 @@ declare <2 x half> @_Z3powDv2_DhS_(<2 x half>, <2 x half>)
438438
; GCN: %1 = bitcast half %x to i16
439439
; GCN: %__pow_sign = and i16 %1, -32768
440440
; GCN: %2 = bitcast half %__exp2 to i16
441-
; GCN: %3 = or i16 %__pow_sign, %2
441+
; GCN: %3 = or disjoint i16 %__pow_sign, %2
442442
; GCN: %4 = bitcast i16 %3 to half
443443
define half @test_pow_fast_f16__y_13(half %x) {
444444
%powr = tail call fast half @_Z3powDhDh(half %x, half 13.0)
@@ -453,7 +453,7 @@ define half @test_pow_fast_f16__y_13(half %x) {
453453
; GCN: %1 = bitcast <2 x half> %x to <2 x i16>
454454
; GCN: %__pow_sign = and <2 x i16> %1, <i16 -32768, i16 -32768>
455455
; GCN: %2 = bitcast <2 x half> %__exp2 to <2 x i16>
456-
; GCN: %3 = or <2 x i16> %__pow_sign, %2
456+
; GCN: %3 = or disjoint <2 x i16> %__pow_sign, %2
457457
; GCN: %4 = bitcast <2 x i16> %3 to <2 x half>
458458
define <2 x half> @test_pow_fast_v2f16__y_13(<2 x half> %x) {
459459
%powr = tail call fast <2 x half> @_Z3powDv2_DhS_(<2 x half> %x, <2 x half> <half 13.0, half 13.0>)

‎llvm/test/Transforms/InstCombine/known-bits.ll

Lines changed: 10 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -1001,10 +1001,7 @@ define i1 @extract_value_smul_fail(i8 %xx, i8 %yy) {
10011001

10021002
define i1 @test_sign_pos(float %x) {
10031003
; CHECK-LABEL: @test_sign_pos(
1004-
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
1005-
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[FABS]] to i32
1006-
; CHECK-NEXT: [[SIGN:%.*]] = icmp sgt i32 [[Y]], -1
1007-
; CHECK-NEXT: ret i1 [[SIGN]]
1004+
; CHECK-NEXT: ret i1 true
10081005
;
10091006
%fabs = call float @llvm.fabs.f32(float %x)
10101007
%y = bitcast float %fabs to i32
@@ -1014,11 +1011,7 @@ define i1 @test_sign_pos(float %x) {
10141011

10151012
define i1 @test_sign_neg(float %x) {
10161013
; CHECK-LABEL: @test_sign_neg(
1017-
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
1018-
; CHECK-NEXT: [[FNABS:%.*]] = fneg float [[FABS]]
1019-
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[FNABS]] to i32
1020-
; CHECK-NEXT: [[SIGN:%.*]] = icmp slt i32 [[Y]], 0
1021-
; CHECK-NEXT: ret i1 [[SIGN]]
1014+
; CHECK-NEXT: ret i1 true
10221015
;
10231016
%fabs = call float @llvm.fabs.f32(float %x)
10241017
%fnabs = fneg float %fabs
@@ -1029,10 +1022,7 @@ define i1 @test_sign_neg(float %x) {
10291022

10301023
define <2 x i1> @test_sign_pos_vec(<2 x float> %x) {
10311024
; CHECK-LABEL: @test_sign_pos_vec(
1032-
; CHECK-NEXT: [[FABS:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[X:%.*]])
1033-
; CHECK-NEXT: [[Y:%.*]] = bitcast <2 x float> [[FABS]] to <2 x i32>
1034-
; CHECK-NEXT: [[SIGN:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
1035-
; CHECK-NEXT: ret <2 x i1> [[SIGN]]
1025+
; CHECK-NEXT: ret <2 x i1> zeroinitializer
10361026
;
10371027
%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %x)
10381028
%y = bitcast <2 x float> %fabs to <2 x i32>
@@ -1042,9 +1032,7 @@ define <2 x i1> @test_sign_pos_vec(<2 x float> %x) {
10421032

10431033
define i32 @test_inf_only(float nofpclass(nan sub norm zero) %x) {
10441034
; CHECK-LABEL: @test_inf_only(
1045-
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
1046-
; CHECK-NEXT: [[AND:%.*]] = bitcast float [[TMP1]] to i32
1047-
; CHECK-NEXT: ret i32 [[AND]]
1035+
; CHECK-NEXT: ret i32 2130706432
10481036
;
10491037
%y = bitcast float %x to i32
10501038
%and = and i32 %y, 2147483647
@@ -1053,9 +1041,7 @@ define i32 @test_inf_only(float nofpclass(nan sub norm zero) %x) {
10531041

10541042
define i32 @test_zero_only(float nofpclass(nan sub norm inf) %x) {
10551043
; CHECK-LABEL: @test_zero_only(
1056-
; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])
1057-
; CHECK-NEXT: [[AND:%.*]] = bitcast float [[TMP1]] to i32
1058-
; CHECK-NEXT: ret i32 [[AND]]
1044+
; CHECK-NEXT: ret i32 0
10591045
;
10601046
%y = bitcast float %x to i32
10611047
%and = and i32 %y, 2147483647
@@ -1075,9 +1061,7 @@ define i80 @test_zero_only_non_ieee(x86_fp80 nofpclass(nan sub norm inf) %x) {
10751061

10761062
define i32 @test_inf_nan_only(float nofpclass(sub norm zero) %x) {
10771063
; CHECK-LABEL: @test_inf_nan_only(
1078-
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[X:%.*]] to i32
1079-
; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y]], 2130706432
1080-
; CHECK-NEXT: ret i32 [[AND]]
1064+
; CHECK-NEXT: ret i32 2130706432
10811065
;
10821066
%y = bitcast float %x to i32
10831067
%and = and i32 %y, 2130706432
@@ -1086,9 +1070,7 @@ define i32 @test_inf_nan_only(float nofpclass(sub norm zero) %x) {
10861070

10871071
define i32 @test_sub_zero_only(float nofpclass(nan norm inf) %x) {
10881072
; CHECK-LABEL: @test_sub_zero_only(
1089-
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[X:%.*]] to i32
1090-
; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y]], 2130706432
1091-
; CHECK-NEXT: ret i32 [[AND]]
1073+
; CHECK-NEXT: ret i32 0
10921074
;
10931075
%y = bitcast float %x to i32
10941076
%and = and i32 %y, 2130706432
@@ -1097,9 +1079,7 @@ define i32 @test_sub_zero_only(float nofpclass(nan norm inf) %x) {
10971079

10981080
define i32 @test_inf_zero_only(float nofpclass(nan norm sub) %x) {
10991081
; CHECK-LABEL: @test_inf_zero_only(
1100-
; CHECK-NEXT: [[Y:%.*]] = bitcast float [[X:%.*]] to i32
1101-
; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y]], 16777215
1102-
; CHECK-NEXT: ret i32 [[AND]]
1082+
; CHECK-NEXT: ret i32 0
11031083
;
11041084
%y = bitcast float %x to i32
11051085
%and = and i32 %y, 16777215
@@ -1108,11 +1088,7 @@ define i32 @test_inf_zero_only(float nofpclass(nan norm sub) %x) {
11081088

11091089
define i1 @test_simplify_icmp(i32 %x) {
11101090
; CHECK-LABEL: @test_simplify_icmp(
1111-
; CHECK-NEXT: [[CAST1:%.*]] = uitofp i32 [[X:%.*]] to double
1112-
; CHECK-NEXT: [[CAST2:%.*]] = bitcast double [[CAST1]] to i64
1113-
; CHECK-NEXT: [[MASK:%.*]] = and i64 [[CAST2]], -140737488355328
1114-
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[MASK]], -1970324836974592
1115-
; CHECK-NEXT: ret i1 [[CMP]]
1091+
; CHECK-NEXT: ret i1 false
11161092
;
11171093
%cast1 = uitofp i32 %x to double
11181094
%cast2 = bitcast double %cast1 to i64
@@ -1127,12 +1103,7 @@ define i16 @test_simplify_mask(i32 %ui, float %x) {
11271103
; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[CONV]], [[X:%.*]]
11281104
; CHECK-NEXT: br i1 [[CMP]], label [[IF_ELSE:%.*]], label [[IF_END:%.*]]
11291105
; CHECK: if.end:
1130-
; CHECK-NEXT: [[CAST:%.*]] = bitcast float [[CONV]] to i32
1131-
; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[CAST]], 16
1132-
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHR]] to i16
1133-
; CHECK-NEXT: [[AND:%.*]] = and i16 [[TRUNC]], -32768
1134-
; CHECK-NEXT: [[OR:%.*]] = or disjoint i16 [[AND]], 31744
1135-
; CHECK-NEXT: ret i16 [[OR]]
1106+
; CHECK-NEXT: ret i16 31744
11361107
; CHECK: if.else:
11371108
; CHECK-NEXT: ret i16 0
11381109
;

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