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[X86][SSE] Ensure vector partial load/stores use the WriteVecLoad/WriteVecStore scheduler classes
Retag some instructions that were missed when we split off vector load/store/moves - MOVQ/MOVD etc. Fixes BtVer2/SLM which have different behaviours for GPR stores. llvm-svn: 332718
1 parent a840a46 commit c4b8d36

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12 files changed

+49
-77
lines changed

12 files changed

+49
-77
lines changed

‎llvm/lib/Target/X86/X86InstrAVX512.td

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -3622,7 +3622,7 @@ def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$s
36223622
"vmovd\t{$src, $dst|$dst, $src}",
36233623
[(set VR128X:$dst,
36243624
(v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
3625-
EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteLoad]>;
3625+
EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecLoad]>;
36263626
def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
36273627
"vmovq\t{$src, $dst|$dst, $src}",
36283628
[(set VR128X:$dst,
@@ -3632,7 +3632,7 @@ let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
36323632
def VMOV64toPQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
36333633
(ins i64mem:$src),
36343634
"vmovq\t{$src, $dst|$dst, $src}", []>,
3635-
EVEX, VEX_W, EVEX_CD8<64, CD8VT1>, Sched<[WriteLoad]>;
3635+
EVEX, VEX_W, EVEX_CD8<64, CD8VT1>, Sched<[WriteVecLoad]>;
36363636
let isCodeGenOnly = 1 in {
36373637
def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64X:$dst), (ins GR64:$src),
36383638
"vmovq\t{$src, $dst|$dst, $src}",
@@ -3641,15 +3641,15 @@ def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64X:$dst), (ins GR64:$src)
36413641
def VMOV64toSDZrm : AVX512XSI<0x7E, MRMSrcMem, (outs FR64X:$dst), (ins i64mem:$src),
36423642
"vmovq\t{$src, $dst|$dst, $src}",
36433643
[(set FR64X:$dst, (bitconvert (loadi64 addr:$src)))]>,
3644-
EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteLoad]>;
3644+
EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteVecLoad]>;
36453645
def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64X:$src),
36463646
"vmovq\t{$src, $dst|$dst, $src}",
36473647
[(set GR64:$dst, (bitconvert FR64X:$src))]>,
36483648
EVEX, VEX_W, Sched<[WriteMove]>;
36493649
def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64X:$src),
36503650
"vmovq\t{$src, $dst|$dst, $src}",
36513651
[(store (i64 (bitconvert FR64X:$src)), addr:$dst)]>,
3652-
EVEX, VEX_W, Sched<[WriteStore]>,
3652+
EVEX, VEX_W, Sched<[WriteVecStore]>,
36533653
EVEX_CD8<64, CD8VT1>;
36543654
}
36553655
} // ExeDomain = SSEPackedInt
@@ -3665,7 +3665,7 @@ def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src)
36653665
def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
36663666
"vmovd\t{$src, $dst|$dst, $src}",
36673667
[(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))]>,
3668-
EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteLoad]>;
3668+
EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecLoad]>;
36693669
} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
36703670

36713671
// Move doubleword from xmm register to r/m32
@@ -3681,7 +3681,7 @@ def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
36813681
"vmovd\t{$src, $dst|$dst, $src}",
36823682
[(store (i32 (extractelt (v4i32 VR128X:$src),
36833683
(iPTR 0))), addr:$dst)]>,
3684-
EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteStore]>;
3684+
EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecStore]>;
36853685
} // ExeDomain = SSEPackedInt
36863686

36873687
// Move quadword from xmm1 register to r/m64
@@ -3697,7 +3697,7 @@ def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
36973697
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
36983698
def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128X:$src),
36993699
"vmovq\t{$src, $dst|$dst, $src}", []>, PD,
3700-
EVEX, VEX_W, Sched<[WriteStore]>,
3700+
EVEX, VEX_W, Sched<[WriteVecStore]>,
37013701
Requires<[HasAVX512, In64BitMode]>;
37023702

37033703
def VMOVPQI2QIZmr : I<0xD6, MRMDestMem, (outs),
@@ -3706,7 +3706,7 @@ def VMOVPQI2QIZmr : I<0xD6, MRMDestMem, (outs),
37063706
[(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
37073707
addr:$dst)]>,
37083708
EVEX, PD, VEX_W, EVEX_CD8<64, CD8VT1>,
3709-
Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
3709+
Sched<[WriteVecStore]>, Requires<[HasAVX512, In64BitMode]>;
37103710

37113711
let hasSideEffects = 0 in
37123712
def VMOVPQI2QIZrr : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst),
@@ -3727,7 +3727,7 @@ def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
37273727
(ins i32mem:$dst, FR32X:$src),
37283728
"vmovd\t{$src, $dst|$dst, $src}",
37293729
[(store (i32 (bitconvert FR32X:$src)), addr:$dst)]>,
3730-
EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteStore]>;
3730+
EVEX, EVEX_CD8<32, CD8VT1>, Sched<[WriteVecStore]>;
37313731
} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
37323732

37333733
// Move Quadword Int to Packed Quadword Int
@@ -3738,7 +3738,7 @@ def VMOVQI2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
37383738
"vmovq\t{$src, $dst|$dst, $src}",
37393739
[(set VR128X:$dst,
37403740
(v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
3741-
EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteLoad]>;
3741+
EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteVecLoad]>;
37423742
} // ExeDomain = SSEPackedInt
37433743

37443744
// Allow "vmovd" but print "vmovq".

‎llvm/lib/Target/X86/X86InstrMMX.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -170,7 +170,7 @@ def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
170170
"movd\t{$src, $dst|$dst, $src}",
171171
[(set VR64:$dst,
172172
(x86mmx (scalar_to_vector (loadi32 addr:$src))))]>,
173-
Sched<[WriteLoad]>;
173+
Sched<[WriteVecLoad]>;
174174

175175
let Predicates = [HasMMX] in {
176176
let AddedComplexity = 15 in
@@ -187,7 +187,7 @@ let Predicates = [HasMMX] in {
187187
let mayStore = 1 in
188188
def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
189189
"movd\t{$src, $dst|$dst, $src}", []>,
190-
Sched<[WriteStore]>;
190+
Sched<[WriteVecStore]>;
191191

192192
def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src),
193193
"movd\t{$src, $dst|$dst, $src}",

‎llvm/lib/Target/X86/X86InstrSSE.td

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -3970,7 +3970,7 @@ def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
39703970
"movd\t{$src, $dst|$dst, $src}",
39713971
[(set VR128:$dst,
39723972
(v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
3973-
VEX, Sched<[WriteLoad]>;
3973+
VEX, Sched<[WriteVecLoad]>;
39743974
def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
39753975
"movq\t{$src, $dst|$dst, $src}",
39763976
[(set VR128:$dst,
@@ -3979,7 +3979,7 @@ def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
39793979
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
39803980
def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
39813981
"movq\t{$src, $dst|$dst, $src}", []>,
3982-
VEX, Sched<[WriteLoad]>;
3982+
VEX, Sched<[WriteVecLoad]>;
39833983
let isCodeGenOnly = 1 in
39843984
def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
39853985
"movq\t{$src, $dst|$dst, $src}",
@@ -3995,7 +3995,7 @@ def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
39953995
"movd\t{$src, $dst|$dst, $src}",
39963996
[(set VR128:$dst,
39973997
(v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
3998-
Sched<[WriteLoad]>;
3998+
Sched<[WriteVecLoad]>;
39993999
def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
40004000
"movq\t{$src, $dst|$dst, $src}",
40014001
[(set VR128:$dst,
@@ -4004,7 +4004,7 @@ def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
40044004
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
40054005
def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
40064006
"movq\t{$src, $dst|$dst, $src}", []>,
4007-
Sched<[WriteLoad]>;
4007+
Sched<[WriteVecLoad]>;
40084008
let isCodeGenOnly = 1 in
40094009
def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
40104010
"movq\t{$src, $dst|$dst, $src}",
@@ -4024,7 +4024,7 @@ let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in {
40244024
def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
40254025
"movd\t{$src, $dst|$dst, $src}",
40264026
[(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
4027-
VEX, Sched<[WriteLoad]>;
4027+
VEX, Sched<[WriteVecLoad]>;
40284028
def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
40294029
"movd\t{$src, $dst|$dst, $src}",
40304030
[(set FR32:$dst, (bitconvert GR32:$src))]>,
@@ -4033,7 +4033,7 @@ let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in {
40334033
def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
40344034
"movd\t{$src, $dst|$dst, $src}",
40354035
[(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
4036-
Sched<[WriteLoad]>;
4036+
Sched<[WriteVecLoad]>;
40374037
} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
40384038

40394039
//===---------------------------------------------------------------------===//
@@ -4050,7 +4050,7 @@ def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
40504050
"movd\t{$src, $dst|$dst, $src}",
40514051
[(store (i32 (extractelt (v4i32 VR128:$src),
40524052
(iPTR 0))), addr:$dst)]>,
4053-
VEX, Sched<[WriteStore]>;
4053+
VEX, Sched<[WriteVecStore]>;
40544054
def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
40554055
"movd\t{$src, $dst|$dst, $src}",
40564056
[(set GR32:$dst, (extractelt (v4i32 VR128:$src),
@@ -4060,7 +4060,7 @@ def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
40604060
"movd\t{$src, $dst|$dst, $src}",
40614061
[(store (i32 (extractelt (v4i32 VR128:$src),
40624062
(iPTR 0))), addr:$dst)]>,
4063-
Sched<[WriteStore]>;
4063+
Sched<[WriteVecStore]>;
40644064
} // ExeDomain = SSEPackedInt
40654065

40664066
//===---------------------------------------------------------------------===//
@@ -4084,11 +4084,11 @@ let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
40844084
def VMOVPQIto64mr : VRS2I<0x7E, MRMDestMem, (outs),
40854085
(ins i64mem:$dst, VR128:$src),
40864086
"movq\t{$src, $dst|$dst, $src}", []>,
4087-
VEX, Sched<[WriteStore]>;
4087+
VEX, Sched<[WriteVecStore]>;
40884088
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
40894089
def MOVPQIto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
40904090
"movq\t{$src, $dst|$dst, $src}", []>,
4091-
Sched<[WriteStore]>;
4091+
Sched<[WriteVecStore]>;
40924092
} // ExeDomain = SSEPackedInt
40934093

40944094
//===---------------------------------------------------------------------===//
@@ -4099,28 +4099,28 @@ let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in {
40994099
def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
41004100
"movq\t{$src, $dst|$dst, $src}",
41014101
[(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4102-
VEX, Sched<[WriteLoad]>;
4102+
VEX, Sched<[WriteVecLoad]>;
41034103
def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
41044104
"movq\t{$src, $dst|$dst, $src}",
41054105
[(set GR64:$dst, (bitconvert FR64:$src))]>,
41064106
VEX, Sched<[WriteMove]>;
41074107
def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
41084108
"movq\t{$src, $dst|$dst, $src}",
41094109
[(store (i64 (bitconvert FR64:$src)), addr:$dst)]>,
4110-
VEX, Sched<[WriteStore]>;
4110+
VEX, Sched<[WriteVecStore]>;
41114111

41124112
def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
41134113
"movq\t{$src, $dst|$dst, $src}",
41144114
[(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4115-
Sched<[WriteLoad]>;
4115+
Sched<[WriteVecLoad]>;
41164116
def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
41174117
"movq\t{$src, $dst|$dst, $src}",
41184118
[(set GR64:$dst, (bitconvert FR64:$src))]>,
41194119
Sched<[WriteMove]>;
41204120
def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
41214121
"movq\t{$src, $dst|$dst, $src}",
41224122
[(store (i64 (bitconvert FR64:$src)), addr:$dst)]>,
4123-
Sched<[WriteStore]>;
4123+
Sched<[WriteVecStore]>;
41244124
} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
41254125

41264126
//===---------------------------------------------------------------------===//
@@ -4134,15 +4134,15 @@ let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in {
41344134
def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
41354135
"movd\t{$src, $dst|$dst, $src}",
41364136
[(store (i32 (bitconvert FR32:$src)), addr:$dst)]>,
4137-
VEX, Sched<[WriteStore]>;
4137+
VEX, Sched<[WriteVecStore]>;
41384138
def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
41394139
"movd\t{$src, $dst|$dst, $src}",
41404140
[(set GR32:$dst, (bitconvert FR32:$src))]>,
41414141
Sched<[WriteMove]>;
41424142
def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
41434143
"movd\t{$src, $dst|$dst, $src}",
41444144
[(store (i32 (bitconvert FR32:$src)), addr:$dst)]>,
4145-
Sched<[WriteStore]>;
4145+
Sched<[WriteVecStore]>;
41464146
} // ExeDomain = SSEPackedInt, isCodeGenOnly = 1
41474147

41484148
let Predicates = [UseAVX] in {
@@ -4225,7 +4225,7 @@ def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
42254225
// Move Quadword Int to Packed Quadword Int
42264226
//
42274227

4228-
let ExeDomain = SSEPackedInt, SchedRW = [WriteLoad] in {
4228+
let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLoad] in {
42294229
def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
42304230
"vmovq\t{$src, $dst|$dst, $src}",
42314231
[(set VR128:$dst,
@@ -4241,7 +4241,7 @@ def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
42414241
//===---------------------------------------------------------------------===//
42424242
// Move Packed Quadword Int to Quadword Int
42434243
//
4244-
let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4244+
let ExeDomain = SSEPackedInt, SchedRW = [WriteVecStore] in {
42454245
def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
42464246
"movq\t{$src, $dst|$dst, $src}",
42474247
[(store (i64 (extractelt (v2i64 VR128:$src),

‎llvm/lib/Target/X86/X86SchedBroadwell.td

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -600,13 +600,7 @@ def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
600600
let ResourceCycles = [1,1];
601601
}
602602
def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
603-
"MMX_MOVD64mr",
604-
"ST_FP(32|64|80)m",
605-
"(V?)MOV(H|L)(PD|PS)mr",
606-
"(V?)MOVPDI2DImr",
607-
"(V?)MOVPQI2QImr",
608-
"(V?)MOVPQIto64mr",
609-
"(V?)MOV(SD|SS)mr")>;
603+
"ST_FP(32|64|80)m")>;
610604

611605
def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
612606
let Latency = 2;

‎llvm/lib/Target/X86/X86SchedHaswell.td

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -786,13 +786,7 @@ def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> {
786786
let ResourceCycles = [1,1];
787787
}
788788
def: InstRW<[HWWriteResGroup1], (instregex "FBSTPm",
789-
"MMX_MOVD64mr",
790789
"ST_FP(32|64|80)m",
791-
"(V?)MOV(H|L)(PD|PS)mr",
792-
"(V?)MOVPDI2DImr",
793-
"(V?)MOVPQI2QImr",
794-
"(V?)MOVPQIto64mr",
795-
"(V?)MOV(SD|SS)mr",
796790
"VMPTRSTm")>;
797791

798792
def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {

‎llvm/lib/Target/X86/X86SchedSkylakeClient.td

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -602,13 +602,7 @@ def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
602602
let ResourceCycles = [1,1];
603603
}
604604
def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm",
605-
"MMX_MOVD64mr",
606605
"ST_FP(32|64|80)m",
607-
"(V?)MOV(H|L)(PD|PS)mr",
608-
"(V?)MOVPDI2DImr",
609-
"(V?)MOVPQI2QImr",
610-
"(V?)MOVPQIto64mr",
611-
"(V?)MOV(SD|SS)mr",
612606
"VMPTRSTm")>;
613607

614608
def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0]> {

‎llvm/lib/Target/X86/X86SchedSkylakeServer.td

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -627,17 +627,7 @@ def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
627627
}
628628
def: InstRW<[SKXWriteResGroup11], (instregex "FBSTPm",
629629
"KMOV(B|D|Q|W)mk",
630-
"MMX_MOVD64mr",
631630
"ST_FP(32|64|80)m",
632-
"VMOV(H|L)(PD|PS)Z128mr(b?)",
633-
"(V?)MOV(H|L)(PD|PS)mr",
634-
"VMOVPDI2DIZmr(b?)",
635-
"(V?)MOVPDI2DImr",
636-
"VMOVPQI(2QI|to64)Zmr(b?)",
637-
"(V?)MOVPQI2QImr",
638-
"(V?)MOVPQIto64mr",
639-
"VMOV(SD|SS)Zmr(b?)",
640-
"(V?)MOV(SD|SS)mr",
641631
"VMPTRSTm")>;
642632

643633
def SKXWriteResGroup12 : SchedWriteRes<[SKXPort0]> {

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