[fixup] Don't enable the transformation for SME and simplify some code and tests

Author: momchil-velikov

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -1847,8 +1847,8 @@ void AArch64TargetLowering::addTypeForNEON(MVT VT) {
 
 bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT,
                                                           EVT OpVT) const {
-  // Only SVE/SME has a 1:1 mapping from intrinsic -> instruction (whilelo).
-  if (!Subtarget->hasSVEorSME())
+  // Only SVE has a 1:1 mapping from intrinsic -> instruction (whilelo).
+  if (!Subtarget->hasSVE())
     return true;
 
   // We can only support legal predicate result types. We can use the SVE
@@ -20487,7 +20487,7 @@ static SDValue tryCombineWhileLo(SDNode *N,
   if (DCI.isBeforeLegalize())
     return SDValue();
 
-  if (!Subtarget->hasSVE2p1() && !Subtarget->hasSME2())
+  if (!Subtarget->hasSVE2p1())
     return SDValue();
 
   if (!N->hasNUsesOfValue(2, 0))
@@ -20501,13 +20501,13 @@ static SDValue tryCombineWhileLo(SDNode *N,
   SDNode *Lo = *It++;
   SDNode *Hi = *It;
 
-  uint64_t OffLo, OffHi;
   if (Lo->getOpcode() != ISD::EXTRACT_SUBVECTOR ||
-      !isIntImmediate(Lo->getOperand(1).getNode(), OffLo) ||
-      Hi->getOpcode() != ISD::EXTRACT_SUBVECTOR ||
-      !isIntImmediate(Hi->getOperand(1).getNode(), OffHi))
+      Hi->getOpcode() != ISD::EXTRACT_SUBVECTOR)
     return SDValue();
 
+  uint64_t OffLo = Lo->getConstantOperandVal(1);
+  uint64_t OffHi = Hi->getConstantOperandVal(1);
+
   if (OffLo > OffHi) {
     std::swap(Lo, Hi);
     std::swap(OffLo, OffHi);

llvm/test/CodeGen/AArch64/active_lane_mask.ll

@@ -1,6 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme < %s | FileCheck %s
 
 ; == Scalable ==