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change assertions to return false; make other minor changes to pass llvm check
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4 files changed

+40
-33
lines changed

4 files changed

+40
-33
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 26 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -296,10 +296,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
296296
} else if (ST.hasStdExtD()) {
297297
LoadStoreActions.legalForTypesWithMemDesc({{s64, p0, s64, 64}});
298298
}
299-
if (ST.getELen() == 64)
299+
if (ST.hasVInstructions() && ST.getELen() == 64)
300300
LoadStoreActions.legalForTypesWithMemDesc({{nxv1s8, p0, nxv1s8, 8},
301301
{nxv1s16, p0, nxv1s16, 16},
302302
{nxv1s32, p0, nxv1s32, 32}});
303+
303304
if (ST.hasVInstructionsI64())
304305
LoadStoreActions.legalForTypesWithMemDesc({{nxv1s64, p0, nxv1s64, 64},
305306
{nxv2s64, p0, nxv2s64, 64},
@@ -308,9 +309,13 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
308309

309310
LoadStoreActions.widenScalarToNextPow2(0, /* MinSize = */ 8)
310311
.lowerIfMemSizeNotByteSizePow2()
311-
.custom();
312+
.customIf([=](const LegalityQuery &Query) {
313+
LLT Type = Query.Types[0];
314+
return Type.isScalableVector();
315+
})
316+
.clampScalar(0, s32, sXLen)
317+
.lower();
312318

313-
LoadStoreActions.clampScalar(0, s32, sXLen).lower();
314319
ExtLoadActions.widenScalarToNextPow2(0).clampScalar(0, s32, sXLen).lower();
315320

316321
getActionDefinitionsBuilder({G_PTR_ADD, G_PTRMASK}).legalFor({{p0, sXLen}});
@@ -683,24 +688,28 @@ bool RISCVLegalizerInfo::legalizeExt(MachineInstr &MI,
683688
}
684689

685690
bool RISCVLegalizerInfo::legalizeLoadStore(MachineInstr &MI,
691+
LegalizerHelper &Helper,
686692
MachineIRBuilder &MIB) const {
687693
MachineRegisterInfo &MRI = *MIB.getMRI();
688-
MachineFunction *MF = MI.getParent()->getParent();
694+
MachineFunction *MF = MI.getMF();
689695
const DataLayout &DL = MIB.getDataLayout();
690696
LLVMContext &Ctx = MF->getFunction().getContext();
691697

692698
Register DstReg = MI.getOperand(0).getReg();
693699
Register PtrReg = MI.getOperand(1).getReg();
694700
LLT DataTy = MRI.getType(DstReg);
695-
assert(DataTy.isVector() && "Expect vector load.");
696-
assert(STI.hasVInstructions() &&
697-
(DataTy.getScalarSizeInBits() != 64 || STI.hasVInstructionsI64()) &&
698-
(DataTy.getElementCount().getKnownMinValue() != 1 ||
699-
STI.getELen() == 64) &&
700-
"Load type must be legal integer or floating point vector.");
701-
702-
assert(MI.hasOneMemOperand() &&
703-
"Load instructions only have one MemOperand.");
701+
if (!DataTy.isVector())
702+
return false;
703+
704+
if (!(STI.hasVInstructions() &&
705+
(DataTy.getScalarSizeInBits() != 64 || STI.hasVInstructionsI64()) &&
706+
(DataTy.getElementCount().getKnownMinValue() != 1 ||
707+
STI.getELen() == 64)))
708+
return false;
709+
710+
if (!MI.hasOneMemOperand())
711+
return false;
712+
704713
MachineMemOperand *MMO = *MI.memoperands_begin();
705714
Align Alignment = MMO->getAlign();
706715

@@ -724,12 +733,11 @@ bool RISCVLegalizerInfo::legalizeLoadStore(MachineInstr &MI,
724733
MF->getMachineMemOperand(PI, MMO->getFlags(), NewDataTy, Alignment);
725734

726735
if (isa<GLoad>(MI)) {
727-
auto NewLoad = MIB.buildLoad(NewDataTy, PtrReg, *NewMMO);
728-
MIB.buildBitcast(DstReg, NewLoad);
736+
Helper.bitcast(MI, 0, NewDataTy);
729737
} else {
730738
assert(isa<GStore>(MI) && "Machine instructions must be Load/Store.");
731-
auto BitcastedData = MIB.buildBitcast(NewDataTy, DstReg);
732-
MIB.buildStore(BitcastedData, PtrReg, *NewMMO);
739+
Helper.bitcast(MI, 0, NewDataTy);
740+
MIB.buildStore(MI.getOperand(0), PtrReg, *NewMMO);
733741
}
734742

735743
MI.eraseFromParent();
@@ -916,7 +924,7 @@ bool RISCVLegalizerInfo::legalizeCustom(
916924
return legalizeSplatVector(MI, MIRBuilder);
917925
case TargetOpcode::G_LOAD:
918926
case TargetOpcode::G_STORE:
919-
return legalizeLoadStore(MI, MIRBuilder);
927+
return legalizeLoadStore(MI, Helper, MIRBuilder);
920928
}
921929

922930
llvm_unreachable("expected switch to return");

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINELEGALIZER_H
1414
#define LLVM_LIB_TARGET_RISCV_RISCVMACHINELEGALIZER_H
1515

16+
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
1617
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
1718
#include "llvm/CodeGen/Register.h"
1819

@@ -45,7 +46,8 @@ class RISCVLegalizerInfo : public LegalizerInfo {
4546
bool legalizeVScale(MachineInstr &MI, MachineIRBuilder &MIB) const;
4647
bool legalizeExt(MachineInstr &MI, MachineIRBuilder &MIRBuilder) const;
4748
bool legalizeSplatVector(MachineInstr &MI, MachineIRBuilder &MIB) const;
48-
bool legalizeLoadStore(MachineInstr &MI, MachineIRBuilder &MIB) const;
49+
bool legalizeLoadStore(MachineInstr &MI, LegalizerHelper &Helper,
50+
MachineIRBuilder &MIB) const;
4951
};
5052
} // end namespace llvm
5153
#endif

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load.mir

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -725,8 +725,7 @@ body: |
725725
; CHECK: liveins: $x10
726726
; CHECK-NEXT: {{ $}}
727727
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
728-
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s8>) from %ir.pa, align 1)
729-
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 4 x s16>) = G_BITCAST [[LOAD]](<vscale x 8 x s8>)
728+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 4 x s16>) = G_BITCAST %2:_(<vscale x 8 x s8>)
730729
; CHECK-NEXT: $v8 = COPY [[BITCAST]](<vscale x 4 x s16>)
731730
; CHECK-NEXT: PseudoRET implicit $v8
732731
%0:_(p0) = COPY $x10
@@ -821,8 +820,7 @@ body: |
821820
; CHECK: liveins: $x10
822821
; CHECK-NEXT: {{ $}}
823822
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
824-
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s8>) from %ir.pa, align 2)
825-
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x s32>) = G_BITCAST [[LOAD]](<vscale x 8 x s8>)
823+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x s32>) = G_BITCAST %2:_(<vscale x 8 x s8>)
826824
; CHECK-NEXT: $v8 = COPY [[BITCAST]](<vscale x 2 x s32>)
827825
; CHECK-NEXT: PseudoRET implicit $v8
828826
%0:_(p0) = COPY $x10
@@ -917,8 +915,7 @@ body: |
917915
; CHECK: liveins: $x10
918916
; CHECK-NEXT: {{ $}}
919917
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
920-
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 4)
921-
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x s64>) = G_BITCAST [[LOAD]](<vscale x 16 x s8>)
918+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x s64>) = G_BITCAST %2:_(<vscale x 16 x s8>)
922919
; CHECK-NEXT: $v8m2 = COPY [[BITCAST]](<vscale x 2 x s64>)
923920
; CHECK-NEXT: PseudoRET implicit $v8m2
924921
%0:_(p0) = COPY $x10

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-store.mir

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1007,17 +1007,17 @@ body: |
10071007
name: vstore_nx2ptr
10081008
body: |
10091009
bb.1 (%ir-block.0):
1010-
liveins: $v8, $x10
1010+
liveins: $x10, $v8m2
10111011
10121012
; CHECK-LABEL: name: vstore_nx2ptr
1013-
; CHECK: liveins: $v8, $x10
1013+
; CHECK: liveins: $x10, $v8m2
10141014
; CHECK-NEXT: {{ $}}
10151015
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
1016-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x p0>) = COPY $v8
1016+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x p0>) = COPY $v8m2
10171017
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 2 x p0>), [[COPY]](p0) :: (store (<vscale x 2 x p0>) into %ir.pa)
10181018
; CHECK-NEXT: PseudoRET
10191019
%0:_(p0) = COPY $x10
1020-
%1:_(<vscale x 2 x p0>) = COPY $v8
1020+
%1:_(<vscale x 2 x p0>) = COPY $v8m2
10211021
G_STORE %1(<vscale x 2 x p0>), %0(p0) :: (store (<vscale x 2 x p0>) into %ir.pa)
10221022
PseudoRET
10231023
@@ -1026,17 +1026,17 @@ body: |
10261026
name: vstore_nx8ptr
10271027
body: |
10281028
bb.1 (%ir-block.0):
1029-
liveins: $x10, $v8m4
1029+
liveins: $x10, $v8m8
10301030
10311031
; CHECK-LABEL: name: vstore_nx8ptr
1032-
; CHECK: liveins: $x10, $v8m4
1032+
; CHECK: liveins: $x10, $v8m8
10331033
; CHECK-NEXT: {{ $}}
10341034
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
1035-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x p0>) = COPY $v8m4
1035+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x p0>) = COPY $v8m8
10361036
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 8 x p0>), [[COPY]](p0) :: (store (<vscale x 8 x p0>) into %ir.pa)
10371037
; CHECK-NEXT: PseudoRET
10381038
%0:_(p0) = COPY $x10
1039-
%1:_(<vscale x 8 x p0>) = COPY $v8m4
1039+
%1:_(<vscale x 8 x p0>) = COPY $v8m8
10401040
G_STORE %1(<vscale x 8 x p0>), %0(p0) :: (store (<vscale x 8 x p0>) into %ir.pa)
10411041
PseudoRET
10421042

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