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[AMDGPU][CodeGen][test] update mir test file with latest update_mir
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir

Lines changed: 91 additions & 0 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -157,10 +157,8 @@ body: |
157157
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
158158
%cst_1:_(s32) = G_CONSTANT i32 -5
159159
160-
; 000 ... 1011
161160
%cst_11:_(s32) = G_CONSTANT i32 11
162161
163-
; Sext from the 4th bit -> 111 ... 1011 = -5
164162
%sext_inreg_11:_(s32) = G_SEXT_INREG %cst_11, 4
165163
166164
%and:_(s32) = G_AND %cst_1(s32), %sext_inreg_11(s32)

‎llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -37,8 +37,8 @@ body: |
3737
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
3838
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
3939
; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C]](s32)
40-
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[SSHLSAT]](s32)
41-
; CHECK-NEXT: $sgpr0 = COPY [[INT]](s32)
40+
; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[SSHLSAT]](s32)
41+
; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)
4242
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
4343
%0:_(s32) = COPY $sgpr0
4444
%2:_(s32) = G_CONSTANT i32 1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ body: |
2323
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
2424
; GFX6-NEXT: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
2525
; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
26+
;
2627
; GFX10-LABEL: name: add_s16
2728
; GFX10: liveins: $vgpr0, $vgpr1
2829
; GFX10-NEXT: {{ $}}
@@ -56,6 +57,7 @@ body: |
5657
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
5758
; GFX6-NEXT: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
5859
; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
60+
;
5961
; GFX10-LABEL: name: add_s16_zext_to_s32
6062
; GFX10: liveins: $vgpr0, $vgpr1
6163
; GFX10-NEXT: {{ $}}
@@ -91,6 +93,7 @@ body: |
9193
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
9294
; GFX6-NEXT: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
9395
; GFX6-NEXT: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
96+
;
9497
; GFX10-LABEL: name: add_s16_neg_inline_const_64
9598
; GFX10: liveins: $vgpr0
9699
; GFX10-NEXT: {{ $}}
@@ -121,6 +124,7 @@ body: |
121124
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
122125
; GFX6-NEXT: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
123126
; GFX6-NEXT: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
127+
;
124128
; GFX10-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
125129
; GFX10: liveins: $vgpr0
126130
; GFX10-NEXT: {{ $}}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ body: |
1818
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1919
; WAVE64-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
2020
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
21+
;
2122
; WAVE32-LABEL: name: class_s32_vcc_sv
2223
; WAVE32: liveins: $sgpr0, $vgpr0
2324
; WAVE32-NEXT: {{ $}}
@@ -47,6 +48,7 @@ body: |
4748
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
4849
; WAVE64-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
4950
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
51+
;
5052
; WAVE32-LABEL: name: class_s32_vcc_vs
5153
; WAVE32: liveins: $sgpr0, $vgpr0
5254
; WAVE32-NEXT: {{ $}}
@@ -76,6 +78,7 @@ body: |
7678
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
7779
; WAVE64-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
7880
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
81+
;
7982
; WAVE32-LABEL: name: class_s32_vcc_vv
8083
; WAVE32: liveins: $vgpr0, $vgpr1
8184
; WAVE32-NEXT: {{ $}}
@@ -105,6 +108,7 @@ body: |
105108
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
106109
; WAVE64-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
107110
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
111+
;
108112
; WAVE32-LABEL: name: class_s64_vcc_sv
109113
; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
110114
; WAVE32-NEXT: {{ $}}
@@ -135,6 +139,7 @@ body: |
135139
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
136140
; WAVE64-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
137141
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
142+
;
138143
; WAVE32-LABEL: name: class_s64_vcc_vs
139144
; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
140145
; WAVE32-NEXT: {{ $}}
@@ -165,6 +170,7 @@ body: |
165170
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
166171
; WAVE64-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
167172
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
173+
;
168174
; WAVE32-LABEL: name: class_s64_vcc_vv
169175
; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2
170176
; WAVE32-NEXT: {{ $}}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,8 @@ body: |
1616
; CHECK: liveins: $sgpr0
1717
; CHECK-NEXT: {{ $}}
1818
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
19-
; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
20-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
19+
; CHECK-NEXT: [[V_COS_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
20+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_COS_F32_e64_]]
2121
%0:sgpr(s32) = COPY $sgpr0
2222
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0
2323
S_ENDPGM 0, implicit %1
@@ -37,8 +37,8 @@ body: |
3737
; CHECK: liveins: $vgpr0
3838
; CHECK-NEXT: {{ $}}
3939
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
40-
; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
41-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
40+
; CHECK-NEXT: [[V_COS_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
41+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_COS_F32_e64_]]
4242
%0:vgpr(s32) = COPY $vgpr0
4343
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0
4444
S_ENDPGM 0, implicit %1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,8 @@ body: |
1616
; GCN-NEXT: {{ $}}
1717
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
1818
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
19-
; GCN-NEXT: %2:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
20-
; GCN-NEXT: S_ENDPGM 0, implicit %2
19+
; GCN-NEXT: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
20+
; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]]
2121
%0:sgpr(s32) = COPY $sgpr0
2222
%1:vgpr(s32) = COPY $vgpr0
2323
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
@@ -39,8 +39,8 @@ body: |
3939
; GCN-NEXT: {{ $}}
4040
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4141
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
42-
; GCN-NEXT: %2:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
43-
; GCN-NEXT: S_ENDPGM 0, implicit %2
42+
; GCN-NEXT: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
43+
; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]]
4444
%0:vgpr(s32) = COPY $vgpr0
4545
%1:sgpr(s32) = COPY $sgpr0
4646
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
@@ -61,8 +61,8 @@ body: |
6161
; GCN-NEXT: {{ $}}
6262
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
6363
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
64-
; GCN-NEXT: %2:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
65-
; GCN-NEXT: S_ENDPGM 0, implicit %2
64+
; GCN-NEXT: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
65+
; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]]
6666
%0:vgpr(s32) = COPY $vgpr0
6767
%1:vgpr(s32) = COPY $vgpr1
6868
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,8 @@ body: |
1616
; CHECK: liveins: $sgpr0
1717
; CHECK-NEXT: {{ $}}
1818
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
19-
; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
20-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
19+
; CHECK-NEXT: [[V_FRACT_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
20+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FRACT_F32_e64_]]
2121
%0:sgpr(s32) = COPY $sgpr0
2222
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
2323
S_ENDPGM 0, implicit %1
@@ -37,8 +37,8 @@ body: |
3737
; CHECK: liveins: $vgpr0
3838
; CHECK-NEXT: {{ $}}
3939
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
40-
; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
41-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
40+
; CHECK-NEXT: [[V_FRACT_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
41+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FRACT_F32_e64_]]
4242
%0:vgpr(s32) = COPY $vgpr0
4343
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
4444
S_ENDPGM 0, implicit %1
@@ -58,8 +58,8 @@ body: |
5858
; CHECK: liveins: $sgpr0_sgpr1
5959
; CHECK-NEXT: {{ $}}
6060
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
61-
; CHECK-NEXT: %1:vreg_64 = nofpexcept V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
62-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
61+
; CHECK-NEXT: [[V_FRACT_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
62+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FRACT_F64_e64_]]
6363
%0:sgpr(s64) = COPY $sgpr0_sgpr1
6464
%1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
6565
S_ENDPGM 0, implicit %1
@@ -79,8 +79,8 @@ body: |
7979
; CHECK: liveins: $vgpr0_vgpr1
8080
; CHECK-NEXT: {{ $}}
8181
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
82-
; CHECK-NEXT: %1:vreg_64 = nofpexcept V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
83-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
82+
; CHECK-NEXT: [[V_FRACT_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
83+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FRACT_F64_e64_]]
8484
%0:vgpr(s64) = COPY $vgpr0_vgpr1
8585
%1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
8686
S_ENDPGM 0, implicit %1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.groupstaticsize.mir

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@ body: |
1717
; HSAPAL-LABEL: name: groupstaticsize_v
1818
; HSAPAL: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
1919
; HSAPAL-NEXT: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
20+
;
2021
; MESA-LABEL: name: groupstaticsize_v
2122
; MESA: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @llvm.amdgcn.groupstaticsize, implicit $exec
2223
; MESA-NEXT: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
@@ -38,6 +39,7 @@ body: |
3839
; HSAPAL-LABEL: name: groupstaticsize_s
3940
; HSAPAL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
4041
; HSAPAL-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
42+
;
4143
; MESA-LABEL: name: groupstaticsize_s
4244
; MESA: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @llvm.amdgcn.groupstaticsize
4345
; MESA-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,8 @@ body: |
1616
; CHECK: liveins: $sgpr0
1717
; CHECK-NEXT: {{ $}}
1818
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
19-
; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
20-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
19+
; CHECK-NEXT: [[V_RCP_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
20+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_RCP_F32_e64_]]
2121
%0:sgpr(s32) = COPY $sgpr0
2222
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
2323
S_ENDPGM 0, implicit %1
@@ -37,8 +37,8 @@ body: |
3737
; CHECK: liveins: $vgpr0
3838
; CHECK-NEXT: {{ $}}
3939
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
40-
; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
41-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
40+
; CHECK-NEXT: [[V_RCP_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
41+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_RCP_F32_e64_]]
4242
%0:vgpr(s32) = COPY $vgpr0
4343
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
4444
S_ENDPGM 0, implicit %1
@@ -58,8 +58,8 @@ body: |
5858
; CHECK: liveins: $sgpr0_sgpr1
5959
; CHECK-NEXT: {{ $}}
6060
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
61-
; CHECK-NEXT: %1:vreg_64 = nofpexcept V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
62-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
61+
; CHECK-NEXT: [[V_RCP_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
62+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_RCP_F64_e64_]]
6363
%0:sgpr(s64) = COPY $sgpr0_sgpr1
6464
%1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
6565
S_ENDPGM 0, implicit %1
@@ -79,8 +79,8 @@ body: |
7979
; CHECK: liveins: $vgpr0_vgpr1
8080
; CHECK-NEXT: {{ $}}
8181
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
82-
; CHECK-NEXT: %1:vreg_64 = nofpexcept V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
83-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
82+
; CHECK-NEXT: [[V_RCP_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
83+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_RCP_F64_e64_]]
8484
%0:vgpr(s64) = COPY $vgpr0_vgpr1
8585
%1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
8686
S_ENDPGM 0, implicit %1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,8 +57,8 @@ body: |
5757
; GCN: liveins: $sgpr0
5858
; GCN-NEXT: {{ $}}
5959
; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
60-
; GCN-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY]](s32)
61-
; GCN-NEXT: S_ENDPGM 0, implicit [[INT]](s32)
60+
; GCN-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY]](s32)
61+
; GCN-NEXT: S_ENDPGM 0, implicit [[INTRINSIC_CONVERGENT]](s32)
6262
%0:sgpr(s32) = COPY $sgpr0
6363
%1:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %0
6464
S_ENDPGM 0, implicit %1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,8 @@ body: |
1616
; CHECK: liveins: $sgpr0
1717
; CHECK-NEXT: {{ $}}
1818
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
19-
; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
20-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
19+
; CHECK-NEXT: [[V_RSQ_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
20+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_RSQ_F32_e64_]]
2121
%0:sgpr(s32) = COPY $sgpr0
2222
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0
2323
S_ENDPGM 0, implicit %1
@@ -37,8 +37,8 @@ body: |
3737
; CHECK: liveins: $vgpr0
3838
; CHECK-NEXT: {{ $}}
3939
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
40-
; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
41-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
40+
; CHECK-NEXT: [[V_RSQ_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
41+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_RSQ_F32_e64_]]
4242
%0:vgpr(s32) = COPY $vgpr0
4343
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0
4444
S_ENDPGM 0, implicit %1
@@ -58,8 +58,8 @@ body: |
5858
; CHECK: liveins: $sgpr0_sgpr1
5959
; CHECK-NEXT: {{ $}}
6060
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
61-
; CHECK-NEXT: %1:vreg_64 = nofpexcept V_RSQ_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
62-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
61+
; CHECK-NEXT: [[V_RSQ_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_RSQ_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
62+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_RSQ_F64_e64_]]
6363
%0:sgpr(s64) = COPY $sgpr0_sgpr1
6464
%1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0
6565
S_ENDPGM 0, implicit %1
@@ -79,8 +79,8 @@ body: |
7979
; CHECK: liveins: $vgpr0_vgpr1
8080
; CHECK-NEXT: {{ $}}
8181
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
82-
; CHECK-NEXT: %1:vreg_64 = nofpexcept V_RSQ_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
83-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
82+
; CHECK-NEXT: [[V_RSQ_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_RSQ_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
83+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_RSQ_F64_e64_]]
8484
%0:vgpr(s64) = COPY $vgpr0_vgpr1
8585
%1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0
8686
S_ENDPGM 0, implicit %1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,8 @@ body: |
1616
; CHECK: liveins: $sgpr0
1717
; CHECK-NEXT: {{ $}}
1818
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
19-
; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
20-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
19+
; CHECK-NEXT: [[V_SIN_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
20+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_SIN_F32_e64_]]
2121
%0:sgpr(s32) = COPY $sgpr0
2222
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0
2323
S_ENDPGM 0, implicit %1
@@ -37,8 +37,8 @@ body: |
3737
; CHECK: liveins: $vgpr0
3838
; CHECK-NEXT: {{ $}}
3939
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
40-
; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
41-
; CHECK-NEXT: S_ENDPGM 0, implicit %1
40+
; CHECK-NEXT: [[V_SIN_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
41+
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_SIN_F32_e64_]]
4242
%0:vgpr(s32) = COPY $vgpr0
4343
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0
4444
S_ENDPGM 0, implicit %1

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