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[AArch64] Add addp from shuffles tests. NFC
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‎llvm/test/CodeGen/AArch64/addp-shuffle.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
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; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
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define <4 x i32> @deinterleave_shuffle_v8i32(<8 x i32> %a) {
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; CHECK-LABEL: deinterleave_shuffle_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 v2.4s, v0.4s, v1.4s
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; CHECK-NEXT: uzp2 v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: add v0.4s, v2.4s, v0.4s
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; CHECK-NEXT: ret
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%r0 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%r1 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%o = add <4 x i32> %r0, %r1
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ret <4 x i32> %o
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}
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define <4 x i32> @deinterleave_shuffle_v8i32_c(<8 x i32> %a) {
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; CHECK-LABEL: deinterleave_shuffle_v8i32_c:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 v2.4s, v0.4s, v1.4s
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; CHECK-NEXT: uzp2 v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: add v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: ret
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%r0 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%r1 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%o = add <4 x i32> %r1, %r0
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ret <4 x i32> %o
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}
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define <2 x i32> @deinterleave_shuffle_v4i32(<4 x i32> %a) {
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; CHECK-LABEL: deinterleave_shuffle_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: zip1 v2.2s, v0.2s, v1.2s
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; CHECK-NEXT: zip2 v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: add v0.2s, v2.2s, v0.2s
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; CHECK-NEXT: ret
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%r0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
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%r1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
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%o = add <2 x i32> %r0, %r1
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ret <2 x i32> %o
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}
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define <8 x i16> @deinterleave_shuffle_v16i16(<16 x i16> %a) {
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; CHECK-LABEL: deinterleave_shuffle_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 v2.8h, v0.8h, v1.8h
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; CHECK-NEXT: uzp2 v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: add v0.8h, v2.8h, v0.8h
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; CHECK-NEXT: ret
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%r0 = shufflevector <16 x i16> %a, <16 x i16> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%r1 = shufflevector <16 x i16> %a, <16 x i16> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%o = add <8 x i16> %r0, %r1
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ret <8 x i16> %o
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}
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define <16 x i8> @deinterleave_shuffle_v32i8(<32 x i8> %a) {
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; CHECK-LABEL: deinterleave_shuffle_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 v2.16b, v0.16b, v1.16b
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; CHECK-NEXT: uzp2 v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: add v0.16b, v2.16b, v0.16b
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; CHECK-NEXT: ret
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%r0 = shufflevector <32 x i8> %a, <32 x i8> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
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%r1 = shufflevector <32 x i8> %a, <32 x i8> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
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%o = add <16 x i8> %r0, %r1
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ret <16 x i8> %o
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}
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define <4 x i64> @deinterleave_shuffle_v8i64(<8 x i64> %a) {
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; CHECK-LABEL: deinterleave_shuffle_v8i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: zip1 v4.2d, v2.2d, v3.2d
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; CHECK-NEXT: zip1 v5.2d, v0.2d, v1.2d
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; CHECK-NEXT: zip2 v2.2d, v2.2d, v3.2d
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; CHECK-NEXT: zip2 v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: add v1.2d, v4.2d, v2.2d
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; CHECK-NEXT: add v0.2d, v5.2d, v0.2d
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; CHECK-NEXT: ret
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%r0 = shufflevector <8 x i64> %a, <8 x i64> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%r1 = shufflevector <8 x i64> %a, <8 x i64> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%o = add <4 x i64> %r0, %r1
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ret <4 x i64> %o
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}
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define <4 x float> @deinterleave_shuffle_v8f32(<8 x float> %a) {
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; CHECK-LABEL: deinterleave_shuffle_v8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 v2.4s, v0.4s, v1.4s
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; CHECK-NEXT: uzp2 v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: fadd v0.4s, v2.4s, v0.4s
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; CHECK-NEXT: ret
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%r0 = shufflevector <8 x float> %a, <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%r1 = shufflevector <8 x float> %a, <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%o = fadd <4 x float> %r0, %r1
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ret <4 x float> %o
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}
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define <4 x float> @deinterleave_shuffle_v8f32_c(<8 x float> %a) {
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; CHECK-LABEL: deinterleave_shuffle_v8f32_c:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 v2.4s, v0.4s, v1.4s
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; CHECK-NEXT: uzp2 v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: fadd v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: ret
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%r0 = shufflevector <8 x float> %a, <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%r1 = shufflevector <8 x float> %a, <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%o = fadd <4 x float> %r1, %r0
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ret <4 x float> %o
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}
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define <8 x half> @deinterleave_shuffle_v16f16(<16 x half> %a) {
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; CHECK-NOFP16-LABEL: deinterleave_shuffle_v16f16:
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; CHECK-NOFP16: // %bb.0:
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; CHECK-NOFP16-NEXT: uzp1 v2.8h, v0.8h, v1.8h
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; CHECK-NOFP16-NEXT: uzp2 v0.8h, v0.8h, v1.8h
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; CHECK-NOFP16-NEXT: fcvtl v1.4s, v0.4h
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; CHECK-NOFP16-NEXT: fcvtl v3.4s, v2.4h
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; CHECK-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h
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; CHECK-NOFP16-NEXT: fcvtl2 v2.4s, v2.8h
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; CHECK-NOFP16-NEXT: fadd v1.4s, v3.4s, v1.4s
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; CHECK-NOFP16-NEXT: fadd v2.4s, v2.4s, v0.4s
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; CHECK-NOFP16-NEXT: fcvtn v0.4h, v1.4s
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; CHECK-NOFP16-NEXT: fcvtn2 v0.8h, v2.4s
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; CHECK-NOFP16-NEXT: ret
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;
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; CHECK-FP16-LABEL: deinterleave_shuffle_v16f16:
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; CHECK-FP16: // %bb.0:
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; CHECK-FP16-NEXT: uzp1 v2.8h, v0.8h, v1.8h
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; CHECK-FP16-NEXT: uzp2 v0.8h, v0.8h, v1.8h
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; CHECK-FP16-NEXT: fadd v0.8h, v2.8h, v0.8h
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; CHECK-FP16-NEXT: ret
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%r0 = shufflevector <16 x half> %a, <16 x half> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%r1 = shufflevector <16 x half> %a, <16 x half> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%o = fadd <8 x half> %r0, %r1
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ret <8 x half> %o
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}
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define <4 x double> @deinterleave_shuffle_v8f64(<8 x double> %a) {
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; CHECK-LABEL: deinterleave_shuffle_v8f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: zip1 v4.2d, v2.2d, v3.2d
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; CHECK-NEXT: zip1 v5.2d, v0.2d, v1.2d
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; CHECK-NEXT: zip2 v2.2d, v2.2d, v3.2d
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; CHECK-NEXT: zip2 v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: fadd v1.2d, v4.2d, v2.2d
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; CHECK-NEXT: fadd v0.2d, v5.2d, v0.2d
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; CHECK-NEXT: ret
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%r0 = shufflevector <8 x double> %a, <8 x double> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%r1 = shufflevector <8 x double> %a, <8 x double> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%o = fadd <4 x double> %r0, %r1
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ret <4 x double> %o
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}
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define <4 x i32> @udot(<4 x i32> %z, <16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: udot:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v3.8h, v1.8b, #0
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; CHECK-NEXT: ushll v4.8h, v2.8b, #0
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; CHECK-NEXT: ushll2 v1.8h, v1.16b, #0
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; CHECK-NEXT: ushll2 v2.8h, v2.16b, #0
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; CHECK-NEXT: umull2 v5.4s, v3.8h, v4.8h
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; CHECK-NEXT: umull v3.4s, v3.4h, v4.4h
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; CHECK-NEXT: umull2 v4.4s, v1.8h, v2.8h
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; CHECK-NEXT: umull v1.4s, v1.4h, v2.4h
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; CHECK-NEXT: uzp1 v2.4s, v3.4s, v5.4s
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; CHECK-NEXT: uzp2 v3.4s, v3.4s, v5.4s
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; CHECK-NEXT: uzp1 v6.4s, v1.4s, v4.4s
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; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
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; CHECK-NEXT: add v2.4s, v2.4s, v3.4s
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; CHECK-NEXT: add v1.4s, v6.4s, v1.4s
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; CHECK-NEXT: uzp1 v3.4s, v2.4s, v1.4s
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; CHECK-NEXT: uzp2 v1.4s, v2.4s, v1.4s
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; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%za = zext <16 x i8> %a to <16 x i32>
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%zb = zext <16 x i8> %b to <16 x i32>
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%m = mul <16 x i32> %za, %zb
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%r0 = shufflevector <16 x i32> %m, <16 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%r1 = shufflevector <16 x i32> %m, <16 x i32> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%m2 = add <8 x i32> %r0, %r1
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%s0 = shufflevector <8 x i32> %m2, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%s1 = shufflevector <8 x i32> %m2, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%o = add <4 x i32> %s0, %s1
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%n = add <4 x i32> %z, %o
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ret <4 x i32> %n
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}
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define <4 x i32> @sdot(<4 x i32> %z, <16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: sdot:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshll v3.8h, v1.8b, #0
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; CHECK-NEXT: sshll v4.8h, v2.8b, #0
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; CHECK-NEXT: sshll2 v1.8h, v1.16b, #0
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; CHECK-NEXT: sshll2 v2.8h, v2.16b, #0
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; CHECK-NEXT: smull2 v5.4s, v3.8h, v4.8h
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; CHECK-NEXT: smull v3.4s, v3.4h, v4.4h
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; CHECK-NEXT: smull2 v4.4s, v1.8h, v2.8h
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; CHECK-NEXT: smull v1.4s, v1.4h, v2.4h
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; CHECK-NEXT: uzp1 v2.4s, v3.4s, v5.4s
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; CHECK-NEXT: uzp2 v3.4s, v3.4s, v5.4s
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; CHECK-NEXT: uzp1 v6.4s, v1.4s, v4.4s
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; CHECK-NEXT: uzp2 v1.4s, v1.4s, v4.4s
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; CHECK-NEXT: add v2.4s, v2.4s, v3.4s
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; CHECK-NEXT: add v1.4s, v6.4s, v1.4s
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; CHECK-NEXT: uzp1 v3.4s, v2.4s, v1.4s
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; CHECK-NEXT: uzp2 v1.4s, v2.4s, v1.4s
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; CHECK-NEXT: add v1.4s, v3.4s, v1.4s
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%za = sext <16 x i8> %a to <16 x i32>
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%zb = sext <16 x i8> %b to <16 x i32>
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%m = mul <16 x i32> %za, %zb
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%r0 = shufflevector <16 x i32> %m, <16 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%r1 = shufflevector <16 x i32> %m, <16 x i32> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%m2 = add <8 x i32> %r0, %r1
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%s0 = shufflevector <8 x i32> %m2, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%s1 = shufflevector <8 x i32> %m2, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%o = add <4 x i32> %s0, %s1
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%n = add <4 x i32> %z, %o
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ret <4 x i32> %n
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}

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