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[SystemZ] Implement vector rotate in terms of funnel shift
Clang currently implements a set of vector rotate builtins (__builtin_s390_verll*) in terms of platform-specific LLVM intrinsics. To simplify the IR (and allow for common code optimizations if applicable), this patch removes those LLVM intrinsics and implements the builtins in terms of the platform-independent funnel shift intrinsics instead. Also, fix the prototype of the __builtin_s390_verll* builtins for full compatibility with GCC.
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13 files changed

+401
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‎clang/include/clang/Basic/BuiltinsSystemZ.def

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -105,10 +105,10 @@ TARGET_BUILTIN(__builtin_s390_verimb, "V16UcV16UcV16UcV16UcIi", "nc", "vector")
105105
TARGET_BUILTIN(__builtin_s390_verimh, "V8UsV8UsV8UsV8UsIi", "nc", "vector")
106106
TARGET_BUILTIN(__builtin_s390_verimf, "V4UiV4UiV4UiV4UiIi", "nc", "vector")
107107
TARGET_BUILTIN(__builtin_s390_verimg, "V2ULLiV2ULLiV2ULLiV2ULLiIi", "nc", "vector")
108-
TARGET_BUILTIN(__builtin_s390_verllb, "V16UcV16UcUi", "nc", "vector")
109-
TARGET_BUILTIN(__builtin_s390_verllh, "V8UsV8UsUi", "nc", "vector")
110-
TARGET_BUILTIN(__builtin_s390_verllf, "V4UiV4UiUi", "nc", "vector")
111-
TARGET_BUILTIN(__builtin_s390_verllg, "V2ULLiV2ULLiUi", "nc", "vector")
108+
TARGET_BUILTIN(__builtin_s390_verllb, "V16UcV16UcUc", "nc", "vector")
109+
TARGET_BUILTIN(__builtin_s390_verllh, "V8UsV8UsUc", "nc", "vector")
110+
TARGET_BUILTIN(__builtin_s390_verllf, "V4UiV4UiUc", "nc", "vector")
111+
TARGET_BUILTIN(__builtin_s390_verllg, "V2ULLiV2ULLiUc", "nc", "vector")
112112
TARGET_BUILTIN(__builtin_s390_verllvb, "V16UcV16UcV16Uc", "nc", "vector")
113113
TARGET_BUILTIN(__builtin_s390_verllvh, "V8UsV8UsV8Us", "nc", "vector")
114114
TARGET_BUILTIN(__builtin_s390_verllvf, "V4UiV4UiV4Ui", "nc", "vector")

‎clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18337,6 +18337,32 @@ Value *CodeGenFunction::EmitSystemZBuiltinExpr(unsigned BuiltinID,
1833718337
return Builder.CreateCall(F, {X, Undef});
1833818338
}
1833918339

18340+
case SystemZ::BI__builtin_s390_verllb:
18341+
case SystemZ::BI__builtin_s390_verllh:
18342+
case SystemZ::BI__builtin_s390_verllf:
18343+
case SystemZ::BI__builtin_s390_verllg: {
18344+
llvm::Type *ResultType = ConvertType(E->getType());
18345+
llvm::Value *Src = EmitScalarExpr(E->getArg(0));
18346+
llvm::Value *Amt = EmitScalarExpr(E->getArg(1));
18347+
// Splat scalar rotate amount to vector type.
18348+
unsigned NumElts = cast<llvm::FixedVectorType>(ResultType)->getNumElements();
18349+
Amt = Builder.CreateIntCast(Amt, ResultType->getScalarType(), false);
18350+
Amt = Builder.CreateVectorSplat(NumElts, Amt);
18351+
Function *F = CGM.getIntrinsic(Intrinsic::fshl, ResultType);
18352+
return Builder.CreateCall(F, { Src, Src, Amt });
18353+
}
18354+
18355+
case SystemZ::BI__builtin_s390_verllvb:
18356+
case SystemZ::BI__builtin_s390_verllvh:
18357+
case SystemZ::BI__builtin_s390_verllvf:
18358+
case SystemZ::BI__builtin_s390_verllvg: {
18359+
llvm::Type *ResultType = ConvertType(E->getType());
18360+
llvm::Value *Src = EmitScalarExpr(E->getArg(0));
18361+
llvm::Value *Amt = EmitScalarExpr(E->getArg(1));
18362+
Function *F = CGM.getIntrinsic(Intrinsic::fshl, ResultType);
18363+
return Builder.CreateCall(F, { Src, Src, Amt });
18364+
}
18365+
1834018366
case SystemZ::BI__builtin_s390_vfsqsb:
1834118367
case SystemZ::BI__builtin_s390_vfsqdb: {
1834218368
llvm::Type *ResultType = ConvertType(E->getType());

‎clang/lib/Headers/vecintrin.h

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -6565,45 +6565,45 @@ vec_rl(__vector unsigned long long __a, __vector unsigned long long __b) {
65656565
static inline __ATTRS_o_ai __vector signed char
65666566
vec_rli(__vector signed char __a, unsigned long __b) {
65676567
return (__vector signed char)__builtin_s390_verllb(
6568-
(__vector unsigned char)__a, (int)__b);
6568+
(__vector unsigned char)__a, (unsigned char)__b);
65696569
}
65706570

65716571
static inline __ATTRS_o_ai __vector unsigned char
65726572
vec_rli(__vector unsigned char __a, unsigned long __b) {
6573-
return __builtin_s390_verllb(__a, (int)__b);
6573+
return __builtin_s390_verllb(__a, (unsigned char)__b);
65746574
}
65756575

65766576
static inline __ATTRS_o_ai __vector signed short
65776577
vec_rli(__vector signed short __a, unsigned long __b) {
65786578
return (__vector signed short)__builtin_s390_verllh(
6579-
(__vector unsigned short)__a, (int)__b);
6579+
(__vector unsigned short)__a, (unsigned char)__b);
65806580
}
65816581

65826582
static inline __ATTRS_o_ai __vector unsigned short
65836583
vec_rli(__vector unsigned short __a, unsigned long __b) {
6584-
return __builtin_s390_verllh(__a, (int)__b);
6584+
return __builtin_s390_verllh(__a, (unsigned char)__b);
65856585
}
65866586

65876587
static inline __ATTRS_o_ai __vector signed int
65886588
vec_rli(__vector signed int __a, unsigned long __b) {
65896589
return (__vector signed int)__builtin_s390_verllf(
6590-
(__vector unsigned int)__a, (int)__b);
6590+
(__vector unsigned int)__a, (unsigned char)__b);
65916591
}
65926592

65936593
static inline __ATTRS_o_ai __vector unsigned int
65946594
vec_rli(__vector unsigned int __a, unsigned long __b) {
6595-
return __builtin_s390_verllf(__a, (int)__b);
6595+
return __builtin_s390_verllf(__a, (unsigned char)__b);
65966596
}
65976597

65986598
static inline __ATTRS_o_ai __vector signed long long
65996599
vec_rli(__vector signed long long __a, unsigned long __b) {
66006600
return (__vector signed long long)__builtin_s390_verllg(
6601-
(__vector unsigned long long)__a, (int)__b);
6601+
(__vector unsigned long long)__a, (unsigned char)__b);
66026602
}
66036603

66046604
static inline __ATTRS_o_ai __vector unsigned long long
66056605
vec_rli(__vector unsigned long long __a, unsigned long __b) {
6606-
return __builtin_s390_verllg(__a, (int)__b);
6606+
return __builtin_s390_verllg(__a, (unsigned char)__b);
66076607
}
66086608

66096609
/*-- vec_rl_mask ------------------------------------------------------------*/

‎clang/test/CodeGen/SystemZ/builtins-systemz-vector.c

Lines changed: 13 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ volatile vec_ulong vul;
2323
volatile vec_double vd;
2424

2525
volatile unsigned int len;
26+
volatile unsigned char amt;
2627
const void * volatile cptr;
2728
void * volatile ptr;
2829
int cc;
@@ -184,23 +185,23 @@ void test_integer(void) {
184185
vul = __builtin_s390_verimg(vul, vul, vul, 255);
185186
// CHECK: call <2 x i64> @llvm.s390.verimg(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> %{{.*}}, i32 255)
186187

187-
vuc = __builtin_s390_verllb(vuc, len);
188-
// CHECK: call <16 x i8> @llvm.s390.verllb(<16 x i8> %{{.*}}, i32 %{{.*}})
189-
vus = __builtin_s390_verllh(vus, len);
190-
// CHECK: call <8 x i16> @llvm.s390.verllh(<8 x i16> %{{.*}}, i32 %{{.*}})
191-
vui = __builtin_s390_verllf(vui, len);
192-
// CHECK: call <4 x i32> @llvm.s390.verllf(<4 x i32> %{{.*}}, i32 %{{.*}})
193-
vul = __builtin_s390_verllg(vul, len);
194-
// CHECK: call <2 x i64> @llvm.s390.verllg(<2 x i64> %{{.*}}, i32 %{{.*}})
188+
vuc = __builtin_s390_verllb(vuc, amt);
189+
// CHECK: call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}})
190+
vus = __builtin_s390_verllh(vus, amt);
191+
// CHECK: call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}})
192+
vui = __builtin_s390_verllf(vui, amt);
193+
// CHECK: call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
194+
vul = __builtin_s390_verllg(vul, amt);
195+
// CHECK: call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> %{{.*}})
195196

196197
vuc = __builtin_s390_verllvb(vuc, vuc);
197-
// CHECK: call <16 x i8> @llvm.s390.verllvb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}})
198+
// CHECK: call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}})
198199
vus = __builtin_s390_verllvh(vus, vus);
199-
// CHECK: call <8 x i16> @llvm.s390.verllvh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}})
200+
// CHECK: call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}})
200201
vui = __builtin_s390_verllvf(vui, vui);
201-
// CHECK: call <4 x i32> @llvm.s390.verllvf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}})
202+
// CHECK: call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
202203
vul = __builtin_s390_verllvg(vul, vul);
203-
// CHECK: call <2 x i64> @llvm.s390.verllvg(<2 x i64> %{{.*}}, <2 x i64> %{{.*}})
204+
// CHECK: call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> %{{.*}})
204205

205206
vus = __builtin_s390_vgfmb(vuc, vuc);
206207
// CHECK: call <8 x i16> @llvm.s390.vgfmb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}})

‎clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -2564,53 +2564,53 @@ void test_integer(void) {
25642564
// (emulated)
25652565

25662566
vsc = vec_rl(vsc, vuc);
2567-
// CHECK: call <16 x i8> @llvm.s390.verllvb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}})
2567+
// CHECK: call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}})
25682568
// CHECK-ASM: verllvb
25692569
vuc = vec_rl(vuc, vuc);
2570-
// CHECK: call <16 x i8> @llvm.s390.verllvb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}})
2570+
// CHECK: call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}})
25712571
// CHECK-ASM: verllvb
25722572
vss = vec_rl(vss, vus);
2573-
// CHECK: call <8 x i16> @llvm.s390.verllvh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}})
2573+
// CHECK: call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}})
25742574
// CHECK-ASM: verllvh
25752575
vus = vec_rl(vus, vus);
2576-
// CHECK: call <8 x i16> @llvm.s390.verllvh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}})
2576+
// CHECK: call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}})
25772577
// CHECK-ASM: verllvh
25782578
vsi = vec_rl(vsi, vui);
2579-
// CHECK: call <4 x i32> @llvm.s390.verllvf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}})
2579+
// CHECK: call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
25802580
// CHECK-ASM: verllvf
25812581
vui = vec_rl(vui, vui);
2582-
// CHECK: call <4 x i32> @llvm.s390.verllvf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}})
2582+
// CHECK: call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
25832583
// CHECK-ASM: verllvf
25842584
vsl = vec_rl(vsl, vul);
2585-
// CHECK: call <2 x i64> @llvm.s390.verllvg(<2 x i64> %{{.*}}, <2 x i64> %{{.*}})
2585+
// CHECK: call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> %{{.*}})
25862586
// CHECK-ASM: verllvg
25872587
vul = vec_rl(vul, vul);
2588-
// CHECK: call <2 x i64> @llvm.s390.verllvg(<2 x i64> %{{.*}}, <2 x i64> %{{.*}})
2588+
// CHECK: call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> %{{.*}})
25892589
// CHECK-ASM: verllvg
25902590

25912591
vsc = vec_rli(vsc, ul);
2592-
// CHECK: call <16 x i8> @llvm.s390.verllb(<16 x i8> %{{.*}}, i32 %{{.*}})
2592+
// CHECK: call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}})
25932593
// CHECK-ASM: verllb
25942594
vuc = vec_rli(vuc, ul);
2595-
// CHECK: call <16 x i8> @llvm.s390.verllb(<16 x i8> %{{.*}}, i32 %{{.*}})
2595+
// CHECK: call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}})
25962596
// CHECK-ASM: verllb
25972597
vss = vec_rli(vss, ul);
2598-
// CHECK: call <8 x i16> @llvm.s390.verllh(<8 x i16> %{{.*}}, i32 %{{.*}})
2598+
// CHECK: call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}})
25992599
// CHECK-ASM: verllh
26002600
vus = vec_rli(vus, ul);
2601-
// CHECK: call <8 x i16> @llvm.s390.verllh(<8 x i16> %{{.*}}, i32 %{{.*}})
2601+
// CHECK: call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}})
26022602
// CHECK-ASM: verllh
26032603
vsi = vec_rli(vsi, ul);
2604-
// CHECK: call <4 x i32> @llvm.s390.verllf(<4 x i32> %{{.*}}, i32 %{{.*}})
2604+
// CHECK: call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
26052605
// CHECK-ASM: verllf
26062606
vui = vec_rli(vui, ul);
2607-
// CHECK: call <4 x i32> @llvm.s390.verllf(<4 x i32> %{{.*}}, i32 %{{.*}})
2607+
// CHECK: call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
26082608
// CHECK-ASM: verllf
26092609
vsl = vec_rli(vsl, ul);
2610-
// CHECK: call <2 x i64> @llvm.s390.verllg(<2 x i64> %{{.*}}, i32 %{{.*}})
2610+
// CHECK: call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> %{{.*}})
26112611
// CHECK-ASM: verllg
26122612
vul = vec_rli(vul, ul);
2613-
// CHECK: call <2 x i64> @llvm.s390.verllg(<2 x i64> %{{.*}}, i32 %{{.*}})
2613+
// CHECK: call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> %{{.*}})
26142614
// CHECK-ASM: verllg
26152615

26162616
vsc = vec_rl_mask(vsc, vuc, 0);

‎llvm/include/llvm/IR/IntrinsicsSystemZ.td

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -30,10 +30,6 @@ class SystemZBinaryConv<string name, LLVMType result, LLVMType arg>
3030
class SystemZBinary<string name, LLVMType type>
3131
: SystemZBinaryConv<name, type, type>;
3232

33-
class SystemZBinaryInt<string name, LLVMType type>
34-
: ClangBuiltin<"__builtin_s390_" # name>,
35-
Intrinsic<[type], [type, llvm_i32_ty], [IntrNoMem]>;
36-
3733
class SystemZBinaryConvCC<LLVMType result, LLVMType arg>
3834
: Intrinsic<[result, llvm_i32_ty], [arg, arg], [IntrNoMem]>;
3935

@@ -131,13 +127,6 @@ multiclass SystemZBinaryBHFG<string name> : SystemZBinaryBHF<name> {
131127
def g : SystemZBinary<name#"g", llvm_v2i64_ty>;
132128
}
133129

134-
multiclass SystemZBinaryIntBHFG<string name> {
135-
def b : SystemZBinaryInt<name#"b", llvm_v16i8_ty>;
136-
def h : SystemZBinaryInt<name#"h", llvm_v8i16_ty>;
137-
def f : SystemZBinaryInt<name#"f", llvm_v4i32_ty>;
138-
def g : SystemZBinaryInt<name#"g", llvm_v2i64_ty>;
139-
}
140-
141130
multiclass SystemZBinaryCCBHF {
142131
def bs : SystemZBinaryCC<llvm_v16i8_ty>;
143132
def hs : SystemZBinaryCC<llvm_v8i16_ty>;
@@ -303,8 +292,6 @@ let TargetPrefix = "s390" in {
303292
defm int_s390_vmo : SystemZBinaryExtBHF<"vmo">;
304293
defm int_s390_vmlo : SystemZBinaryExtBHF<"vmlo">;
305294

306-
defm int_s390_verllv : SystemZBinaryBHFG<"verllv">;
307-
defm int_s390_verll : SystemZBinaryIntBHFG<"verll">;
308295
defm int_s390_verim : SystemZQuaternaryIntBHFG<"verim">;
309296

310297
def int_s390_vsl : SystemZBinary<"vsl", llvm_v16i8_ty>;

‎llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -385,16 +385,12 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
385385
setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
386386
setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
387387

388-
// Detect shifts by a scalar amount and convert them into
388+
// Detect shifts/rotates by a scalar amount and convert them into
389389
// V*_BY_SCALAR.
390390
setOperationAction(ISD::SHL, VT, Custom);
391391
setOperationAction(ISD::SRA, VT, Custom);
392392
setOperationAction(ISD::SRL, VT, Custom);
393-
394-
// At present ROTL isn't matched by DAGCombiner. ROTR should be
395-
// converted into ROTL.
396-
setOperationAction(ISD::ROTL, VT, Expand);
397-
setOperationAction(ISD::ROTR, VT, Expand);
393+
setOperationAction(ISD::ROTL, VT, Custom);
398394

399395
// Map SETCCs onto one of VCE, VCH or VCHL, swapping the operands
400396
// and inverting the result as necessary.
@@ -5979,6 +5975,8 @@ SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
59795975
return lowerShift(Op, DAG, SystemZISD::VSRL_BY_SCALAR);
59805976
case ISD::SRA:
59815977
return lowerShift(Op, DAG, SystemZISD::VSRA_BY_SCALAR);
5978+
case ISD::ROTL:
5979+
return lowerShift(Op, DAG, SystemZISD::VROTL_BY_SCALAR);
59825980
case ISD::IS_FPCLASS:
59835981
return lowerIS_FPCLASS(Op, DAG);
59845982
case ISD::GET_ROUNDING:
@@ -6143,6 +6141,7 @@ const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
61436141
OPCODE(VSHL_BY_SCALAR);
61446142
OPCODE(VSRL_BY_SCALAR);
61456143
OPCODE(VSRA_BY_SCALAR);
6144+
OPCODE(VROTL_BY_SCALAR);
61466145
OPCODE(VSUM);
61476146
OPCODE(VICMPE);
61486147
OPCODE(VICMPH);

‎llvm/lib/Target/SystemZ/SystemZISelLowering.h

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -215,11 +215,12 @@ enum NodeType : unsigned {
215215
UNPACK_LOW,
216216
UNPACKL_LOW,
217217

218-
// Shift each element of vector operand 0 by the number of bits specified
219-
// by scalar operand 1.
218+
// Shift/rotate each element of vector operand 0 by the number of bits
219+
// specified by scalar operand 1.
220220
VSHL_BY_SCALAR,
221221
VSRL_BY_SCALAR,
222222
VSRA_BY_SCALAR,
223+
VROTL_BY_SCALAR,
223224

224225
// For each element of the output type, sum across all sub-elements of
225226
// operand 0 belonging to the corresponding element, and add in the

‎llvm/lib/Target/SystemZ/SystemZInstrVector.td

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -732,21 +732,17 @@ let Predicates = [FeatureVector] in {
732732

733733
// Element rotate left logical (with vector shift amount).
734734
def VERLLV : BinaryVRRcGeneric<"verllv", 0xE773>;
735-
def VERLLVB : BinaryVRRc<"verllvb", 0xE773, int_s390_verllvb,
736-
v128b, v128b, 0>;
737-
def VERLLVH : BinaryVRRc<"verllvh", 0xE773, int_s390_verllvh,
738-
v128h, v128h, 1>;
739-
def VERLLVF : BinaryVRRc<"verllvf", 0xE773, int_s390_verllvf,
740-
v128f, v128f, 2>;
741-
def VERLLVG : BinaryVRRc<"verllvg", 0xE773, int_s390_verllvg,
742-
v128g, v128g, 3>;
735+
def VERLLVB : BinaryVRRc<"verllvb", 0xE773, rotl, v128b, v128b, 0>;
736+
def VERLLVH : BinaryVRRc<"verllvh", 0xE773, rotl, v128h, v128h, 1>;
737+
def VERLLVF : BinaryVRRc<"verllvf", 0xE773, rotl, v128f, v128f, 2>;
738+
def VERLLVG : BinaryVRRc<"verllvg", 0xE773, rotl, v128g, v128g, 3>;
743739

744740
// Element rotate left logical (with scalar shift amount).
745741
def VERLL : BinaryVRSaGeneric<"verll", 0xE733>;
746-
def VERLLB : BinaryVRSa<"verllb", 0xE733, int_s390_verllb, v128b, v128b, 0>;
747-
def VERLLH : BinaryVRSa<"verllh", 0xE733, int_s390_verllh, v128h, v128h, 1>;
748-
def VERLLF : BinaryVRSa<"verllf", 0xE733, int_s390_verllf, v128f, v128f, 2>;
749-
def VERLLG : BinaryVRSa<"verllg", 0xE733, int_s390_verllg, v128g, v128g, 3>;
742+
def VERLLB : BinaryVRSa<"verllb", 0xE733, z_vrotl_by_scalar, v128b, v128b, 0>;
743+
def VERLLH : BinaryVRSa<"verllh", 0xE733, z_vrotl_by_scalar, v128h, v128h, 1>;
744+
def VERLLF : BinaryVRSa<"verllf", 0xE733, z_vrotl_by_scalar, v128f, v128f, 2>;
745+
def VERLLG : BinaryVRSa<"verllg", 0xE733, z_vrotl_by_scalar, v128g, v128g, 3>;
750746

751747
// Element rotate and insert under mask.
752748
def VERIM : QuaternaryVRIdGeneric<"verim", 0xE772>;

‎llvm/lib/Target/SystemZ/SystemZOperators.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -324,6 +324,8 @@ def z_vsrl_by_scalar : SDNode<"SystemZISD::VSRL_BY_SCALAR",
324324
SDT_ZVecBinaryInt>;
325325
def z_vsra_by_scalar : SDNode<"SystemZISD::VSRA_BY_SCALAR",
326326
SDT_ZVecBinaryInt>;
327+
def z_vrotl_by_scalar : SDNode<"SystemZISD::VROTL_BY_SCALAR",
328+
SDT_ZVecBinaryInt>;
327329
def z_vsum : SDNode<"SystemZISD::VSUM", SDT_ZVecBinaryConv>;
328330
def z_vicmpe : SDNode<"SystemZISD::VICMPE", SDT_ZVecBinary>;
329331
def z_vicmph : SDNode<"SystemZISD::VICMPH", SDT_ZVecBinary>;

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