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[AArch64InstPrinter] Introduce register markup tags emission
AArch64 assembly syntax emission now leverages markup tags for registers, if enabled. Reviewed By: MaskRay, david-arm Differential Revision: https://reviews.llvm.org/D129870
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3 files changed

+98
-49
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‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

Lines changed: 82 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,11 @@ void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
6363
OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
6464
}
6565

66+
void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo,
67+
unsigned AltIdx) const {
68+
OS << markup("<reg:") << getRegisterName(RegNo, AltIdx) << markup(">");
69+
}
70+
6671
void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
6772
StringRef Annot, const MCSubtargetInfo &STI,
6873
raw_ostream &O) {
@@ -112,8 +117,10 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
112117
}
113118

114119
if (AsmMnemonic) {
115-
O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
116-
<< ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
120+
O << '\t' << AsmMnemonic << '\t';
121+
printRegName(O, Op0.getReg());
122+
O << ", ";
123+
printRegName(O, getWRegFromXReg(Op1.getReg()));
117124
printAnnotation(O, Annot);
118125
return;
119126
}
@@ -160,19 +167,23 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
160167

161168
// SBFIZ/UBFIZ aliases
162169
if (Op2.getImm() > Op3.getImm()) {
163-
O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'
164-
<< getRegisterName(Op0.getReg()) << ", "
165-
<< getRegisterName(Op1.getReg()) << ", " << markup("<imm:") << "#"
166-
<< (Is64Bit ? 64 : 32) - Op2.getImm() << markup(">") << ", "
167-
<< markup("<imm:") << "#" << Op3.getImm() + 1 << markup(">");
170+
O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t';
171+
printRegName(O, Op0.getReg());
172+
O << ", ";
173+
printRegName(O, Op1.getReg());
174+
O << ", " << markup("<imm:") << "#" << (Is64Bit ? 64 : 32) - Op2.getImm()
175+
<< markup(">") << ", " << markup("<imm:") << "#" << Op3.getImm() + 1
176+
<< markup(">");
168177
printAnnotation(O, Annot);
169178
return;
170179
}
171180

172181
// Otherwise SBFX/UBFX is the preferred form
173-
O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
174-
<< getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
175-
<< ", " << markup("<imm:") << "#" << Op2.getImm() << markup(">") << ", "
182+
O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t';
183+
printRegName(O, Op0.getReg());
184+
O << ", ";
185+
printRegName(O, Op1.getReg());
186+
O << ", " << markup("<imm:") << "#" << Op2.getImm() << markup(">") << ", "
176187
<< markup("<imm:") << "#" << Op3.getImm() - Op2.getImm() + 1
177188
<< markup(">");
178189
printAnnotation(O, Annot);
@@ -193,9 +204,10 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
193204
int LSB = (BitWidth - ImmR) % BitWidth;
194205
int Width = ImmS + 1;
195206

196-
O << "\tbfc\t" << getRegisterName(Op0.getReg()) << ", " << markup("<imm:")
197-
<< "#" << LSB << markup(">") << ", " << markup("<imm:") << "#" << Width
198-
<< markup(">");
207+
O << "\tbfc\t";
208+
printRegName(O, Op0.getReg());
209+
O << ", " << markup("<imm:") << "#" << LSB << markup(">") << ", "
210+
<< markup("<imm:") << "#" << Width << markup(">");
199211
printAnnotation(O, Annot);
200212
return;
201213
} else if (ImmS < ImmR) {
@@ -204,20 +216,25 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
204216
int LSB = (BitWidth - ImmR) % BitWidth;
205217
int Width = ImmS + 1;
206218

207-
O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
208-
<< getRegisterName(Op2.getReg()) << ", " << markup("<imm:") << "#"
209-
<< LSB << markup(">") << ", " << markup("<imm:") << "#" << Width
210-
<< markup(">");
219+
O << "\tbfi\t";
220+
printRegName(O, Op0.getReg());
221+
O << ", ";
222+
printRegName(O, Op2.getReg());
223+
O << ", " << markup("<imm:") << "#" << LSB << markup(">") << ", "
224+
<< markup("<imm:") << "#" << Width << markup(">");
211225
printAnnotation(O, Annot);
212226
return;
213227
}
214228

215229
int LSB = ImmR;
216230
int Width = ImmS - ImmR + 1;
217231
// Otherwise BFXIL the preferred form
218-
O << "\tbfxil\t" << getRegisterName(Op0.getReg()) << ", "
219-
<< getRegisterName(Op2.getReg()) << ", " << markup("<imm:") << "#" << LSB
220-
<< markup(">") << ", " << markup("<imm:") << "#" << Width << markup(">");
232+
O << "\tbfxil\t";
233+
printRegName(O, Op0.getReg());
234+
O << ", ";
235+
printRegName(O, Op2.getReg());
236+
O << ", " << markup("<imm:") << "#" << LSB << markup(">") << ", "
237+
<< markup("<imm:") << "#" << Width << markup(">");
221238
printAnnotation(O, Annot);
222239
return;
223240
}
@@ -233,17 +250,18 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
233250
else
234251
O << "\tmovn\t";
235252

236-
O << getRegisterName(MI->getOperand(0).getReg()) << ", " << markup("<imm:")
237-
<< "#";
253+
printRegName(O, MI->getOperand(0).getReg());
254+
O << ", " << markup("<imm:") << "#";
238255
MI->getOperand(1).getExpr()->print(O, &MAI);
239256
O << markup(">");
240257
return;
241258
}
242259

243260
if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
244261
MI->getOperand(2).isExpr()) {
245-
O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", "
246-
<< markup("<imm:") << "#";
262+
O << "\tmovk\t";
263+
printRegName(O, MI->getOperand(0).getReg());
264+
O << ", " << markup("<imm:") << "#";
247265
MI->getOperand(2).getExpr()->print(O, &MAI);
248266
O << markup(">");
249267
return;
@@ -262,9 +280,10 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
262280

263281
if (AArch64_AM::isMOVZMovAlias(Value, Shift,
264282
Opcode == AArch64::MOVZXi ? 64 : 32)) {
265-
O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", "
266-
<< markup("<imm:") << "#" << formatImm(SignExtend64(Value, RegWidth))
267-
<< markup(">");
283+
O << "\tmov\t";
284+
printRegName(O, MI->getOperand(0).getReg());
285+
O << ", " << markup("<imm:") << "#"
286+
<< formatImm(SignExtend64(Value, RegWidth)) << markup(">");
268287
return;
269288
}
270289
}
@@ -278,9 +297,10 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
278297
Value = Value & 0xffffffff;
279298

280299
if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
281-
O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", "
282-
<< markup("<imm:") << "#" << formatImm(SignExtend64(Value, RegWidth))
283-
<< markup(">");
300+
O << "\tmov\t";
301+
printRegName(O, MI->getOperand(0).getReg());
302+
O << ", " << markup("<imm:") << "#"
303+
<< formatImm(SignExtend64(Value, RegWidth)) << markup(">");
284304
return;
285305
}
286306
}
@@ -293,9 +313,10 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
293313
uint64_t Value = AArch64_AM::decodeLogicalImmediate(
294314
MI->getOperand(2).getImm(), RegWidth);
295315
if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
296-
O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", "
297-
<< markup("<imm:") << "#" << formatImm(SignExtend64(Value, RegWidth))
298-
<< markup(">");
316+
O << "\tmov\t";
317+
printRegName(O, MI->getOperand(0).getReg());
318+
O << ", " << markup("<imm:") << "#"
319+
<< formatImm(SignExtend64(Value, RegWidth)) << markup(">");
299320
return;
300321
}
301322
}
@@ -737,14 +758,15 @@ void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address,
737758

738759
bool IsTbx;
739760
if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
740-
O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'
741-
<< getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", ";
761+
O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t';
762+
printRegName(O, MI->getOperand(0).getReg(), AArch64::vreg);
763+
O << ", ";
742764

743765
unsigned ListOpNum = IsTbx ? 2 : 1;
744766
printVectorList(MI, ListOpNum, STI, O, "");
745767

746-
O << ", "
747-
<< getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
768+
O << ", ";
769+
printRegName(O, MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
748770
printAnnotation(O, Annot);
749771
return;
750772
}
@@ -762,14 +784,17 @@ void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address,
762784

763785
// Next the address: [xN]
764786
unsigned AddrReg = MI->getOperand(OpNum++).getReg();
765-
O << ", [" << getRegisterName(AddrReg) << ']';
787+
O << ", [";
788+
printRegName(O, AddrReg);
789+
O << ']';
766790

767791
// Finally, there might be a post-indexed offset.
768792
if (LdStDesc->NaturalOffset != 0) {
769793
unsigned Reg = MI->getOperand(OpNum++).getReg();
770-
if (Reg != AArch64::XZR)
771-
O << ", " << getRegisterName(Reg);
772-
else {
794+
if (Reg != AArch64::XZR) {
795+
O << ", ";
796+
printRegName(O, Reg);
797+
} else {
773798
assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
774799
O << ", " << markup("<imm:") << "#" << LdStDesc->NaturalOffset
775800
<< markup(">");
@@ -890,8 +915,10 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
890915
std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
891916

892917
O << '\t' << Str;
893-
if (NeedsReg)
894-
O << ", " << getRegisterName(MI->getOperand(4).getReg());
918+
if (NeedsReg) {
919+
O << ", ";
920+
printRegName(O, MI->getOperand(4).getReg());
921+
}
895922

896923
return true;
897924
}
@@ -1023,7 +1050,7 @@ void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
10231050
const MCOperand &Op = MI->getOperand(OpNo);
10241051
assert(Op.isReg() && "Non-register vreg operand!");
10251052
unsigned Reg = Op.getReg();
1026-
O << getRegisterName(Reg, AArch64::vreg);
1053+
printRegName(O, Reg, AArch64::vreg);
10271054
}
10281055

10291056
void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
@@ -1183,7 +1210,9 @@ void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
11831210
void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
11841211
const MCSubtargetInfo &STI,
11851212
raw_ostream &O) {
1186-
O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
1213+
O << '[';
1214+
printRegName(O, MI->getOperand(OpNum).getReg());
1215+
O << ']';
11871216
}
11881217

11891218
template<int Scale>
@@ -1209,7 +1238,8 @@ void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
12091238
void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
12101239
unsigned Scale, raw_ostream &O) {
12111240
const MCOperand MO1 = MI->getOperand(OpNum + 1);
1212-
O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
1241+
O << '[';
1242+
printRegName(O, MI->getOperand(OpNum).getReg());
12131243
if (MO1.isImm()) {
12141244
O << ", " << markup("<imm:") << "#" << formatImm(MO1.getImm() * Scale)
12151245
<< markup(">");
@@ -1366,7 +1396,9 @@ void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI,
13661396

13671397
unsigned Even = MRI.getSubReg(Reg, Sube);
13681398
unsigned Odd = MRI.getSubReg(Reg, Subo);
1369-
O << getRegisterName(Even) << ", " << getRegisterName(Odd);
1399+
printRegName(O, Even);
1400+
O << ", ";
1401+
printRegName(O, Odd);
13701402
}
13711403

13721404
void AArch64InstPrinter::printMatrixTileList(const MCInst *MI, unsigned OpNum,
@@ -1436,9 +1468,10 @@ void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
14361468

14371469
for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
14381470
if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
1439-
O << getRegisterName(Reg) << LayoutSuffix;
1471+
printRegName(O, Reg);
14401472
else
1441-
O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;
1473+
printRegName(O, Reg, AArch64::vreg);
1474+
O << LayoutSuffix;
14421475

14431476
if (i + 1 != NumRegs)
14441477
O << ", ";

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ class AArch64InstPrinter : public MCInstPrinter {
3030
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
3131
const MCSubtargetInfo &STI, raw_ostream &O) override;
3232
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
33+
void printRegName(raw_ostream &OS, unsigned RegNo, unsigned AltIdx) const;
3334

3435
// Autogenerated by tblgen.
3536
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;

‎llvm/test/MC/Disassembler/AArch64/marked-up.txt

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,3 +12,18 @@
1212
## ls64
1313
# CHECK-NEXT: st64b <reg:x2>, [<reg:x1>]
1414
0x22 0x90 0x3f 0xf8
15+
16+
# CHECK-NEXT: bfi <reg:x4>, <reg:x5>, <imm:#52>, <imm:#11>
17+
0xa4 0x28 0x4c 0xb3
18+
# CHECK-NEXT: bfxil <reg:w9>, <reg:w10>, <imm:#0>, <imm:#1>
19+
0x49 0x1 0x0 0x33
20+
# CHECK-NEXT: sbfiz <reg:x2>, <reg:x3>, <imm:#63>, <imm:#1>
21+
0x62 0x0 0x41 0x93
22+
# CHECK-NEXT: ubfiz <reg:xzr>, <reg:xzr>, <imm:#10>, <imm:#11>
23+
0xff 0x2b 0x76 0xd3
24+
# CHECK-NEXT: sbfx <reg:w12>, <reg:w9>, <imm:#0>, <imm:#1>
25+
0x2c 0x1 0x0 0x13
26+
# CHECK-NEXT: ubfx <reg:xzr>, <reg:x4>, <imm:#0>, <imm:#1>
27+
0x9f 0x0 0x40 0xd3
28+
# CHECK-NEXT: tbx <reg:v0>.8b, { <reg:v6>.16b, <reg:v7>.16b }, <reg:v1>.8b
29+
0xc0 0x30 0x01 0x0e

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