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[AMDGPU] Use range-based for loops. NFC. (#99047)
1 parent 2e56497 commit c7309da

11 files changed

+40
-57
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -190,13 +190,9 @@ class SchedGroup {
190190
// Returns true if the SU matches all rules
191191
bool allowedByRules(const SUnit *SU,
192192
SmallVectorImpl<SchedGroup> &SyncPipe) const {
193-
if (Rules.empty())
194-
return true;
195-
for (size_t I = 0; I < Rules.size(); I++) {
196-
auto TheRule = Rules[I].get();
197-
if (!TheRule->apply(SU, Collection, SyncPipe)) {
193+
for (auto &Rule : Rules) {
194+
if (!Rule.get()->apply(SU, Collection, SyncPipe))
198195
return false;
199-
}
200196
}
201197
return true;
202198
}

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1342,8 +1342,8 @@ SDValue AMDGPUTargetLowering::lowerUnhandledCall(CallLoweringInfo &CLI,
13421342
DAG.getContext()->diagnose(NoCalls);
13431343

13441344
if (!CLI.IsTailCall) {
1345-
for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
1346-
InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
1345+
for (ISD::InputArg &Arg : CLI.Ins)
1346+
InVals.push_back(DAG.getUNDEF(Arg.VT));
13471347
}
13481348

13491349
return DAG.getEntryNode();

‎llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -861,9 +861,8 @@ bool AMDGPULibCalls::TDOFold(CallInst *CI, const FuncInfo &FInfo) {
861861
Constant *nval;
862862
if (getArgType(FInfo) == AMDGPULibFunc::F32) {
863863
SmallVector<float, 0> FVal;
864-
for (unsigned i = 0; i < DVal.size(); ++i) {
865-
FVal.push_back((float)DVal[i]);
866-
}
864+
for (double D : DVal)
865+
FVal.push_back((float)D);
867866
ArrayRef<float> tmp(FVal);
868867
nval = ConstantDataVector::get(context, tmp);
869868
} else { // F64
@@ -1082,9 +1081,8 @@ bool AMDGPULibCalls::fold_pow(FPMathOperator *FPOp, IRBuilder<> &B,
10821081
}
10831082
if (getArgType(FInfo) == AMDGPULibFunc::F32) {
10841083
SmallVector<float, 0> FVal;
1085-
for (unsigned i=0; i < DVal.size(); ++i) {
1086-
FVal.push_back((float)DVal[i]);
1087-
}
1084+
for (double D : DVal)
1085+
FVal.push_back((float)D);
10881086
ArrayRef<float> tmp(FVal);
10891087
cnval = ConstantDataVector::get(M->getContext(), tmp);
10901088
} else {

‎llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -321,8 +321,7 @@ class AMDGPULowerModuleLDS {
321321
ArrayType *KernelOffsetsType = ArrayType::get(I32, Variables.size());
322322

323323
SmallVector<Constant *> Elements;
324-
for (size_t i = 0; i < Variables.size(); i++) {
325-
GlobalVariable *GV = Variables[i];
324+
for (GlobalVariable *GV : Variables) {
326325
auto ConstantGepIt = LDSVarsToConstantGEP.find(GV);
327326
if (ConstantGepIt != LDSVarsToConstantGEP.end()) {
328327
auto elt = ConstantExpr::getPtrToInt(ConstantGepIt->second, I32);
@@ -1194,10 +1193,10 @@ class AMDGPULowerModuleLDS {
11941193
IsPaddingField.reserve(LDSVarsToTransform.size());
11951194
{
11961195
uint64_t CurrentOffset = 0;
1197-
for (size_t I = 0; I < LayoutFields.size(); I++) {
1198-
GlobalVariable *FGV = static_cast<GlobalVariable *>(
1199-
const_cast<void *>(LayoutFields[I].Id));
1200-
Align DataAlign = LayoutFields[I].Alignment;
1196+
for (auto &F : LayoutFields) {
1197+
GlobalVariable *FGV =
1198+
static_cast<GlobalVariable *>(const_cast<void *>(F.Id));
1199+
Align DataAlign = F.Alignment;
12011200

12021201
uint64_t DataAlignV = DataAlign.value();
12031202
if (uint64_t Rem = CurrentOffset % DataAlignV) {
@@ -1218,7 +1217,7 @@ class AMDGPULowerModuleLDS {
12181217

12191218
LocalVars.push_back(FGV);
12201219
IsPaddingField.push_back(false);
1221-
CurrentOffset += LayoutFields[I].Size;
1220+
CurrentOffset += F.Size;
12221221
}
12231222
}
12241223

‎llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -124,10 +124,9 @@ class R600EmitClauseMarkers : public MachineFunctionPass {
124124
assert(
125125
(TII->isALUInstr(MI.getOpcode()) || MI.getOpcode() == R600::DOT_4) &&
126126
"Can't assign Const");
127-
for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
128-
if (Consts[i].first->getReg() != R600::ALU_CONST)
127+
for (auto &[Op, Sel] : Consts) {
128+
if (Op->getReg() != R600::ALU_CONST)
129129
continue;
130-
unsigned Sel = Consts[i].second;
131130
unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31;
132131
unsigned KCacheIndex = Index * 4 + Chan;
133132
const std::pair<unsigned, unsigned> &BankLine = getAccessedBankLine(Sel);
@@ -155,17 +154,16 @@ class R600EmitClauseMarkers : public MachineFunctionPass {
155154
if (!UpdateInstr)
156155
return true;
157156

158-
for (unsigned i = 0, j = 0, n = Consts.size(); i < n; ++i) {
159-
if (Consts[i].first->getReg() != R600::ALU_CONST)
157+
unsigned j = 0;
158+
for (auto &[Op, Sel] : Consts) {
159+
if (Op->getReg() != R600::ALU_CONST)
160160
continue;
161-
switch(UsedKCache[j].first) {
161+
switch (UsedKCache[j].first) {
162162
case 0:
163-
Consts[i].first->setReg(
164-
R600::R600_KC0RegClass.getRegister(UsedKCache[j].second));
163+
Op->setReg(R600::R600_KC0RegClass.getRegister(UsedKCache[j].second));
165164
break;
166165
case 1:
167-
Consts[i].first->setReg(
168-
R600::R600_KC1RegClass.getRegister(UsedKCache[j].second));
166+
Op->setReg(R600::R600_KC1RegClass.getRegister(UsedKCache[j].second));
169167
break;
170168
default:
171169
llvm_unreachable("Wrong Cache Line");

‎llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -669,8 +669,8 @@ void R600MachineCFGStructurizer::wrapup(MachineBasicBlock *MBB) {
669669
}
670670

671671
//delete continue right before endloop
672-
for (unsigned i = 0; i < ContInstr.size(); ++i)
673-
ContInstr[i]->eraseFromParent();
672+
for (auto *MI : ContInstr)
673+
MI->eraseFromParent();
674674

675675
// TODO to fix up jump table so later phase won't be confused. if
676676
// (jumpTableInfo->isEmpty() == false) { need to clean the jump table, but

‎llvm/lib/Target/AMDGPU/R600OpenCLImageTypeLoweringPass.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -244,9 +244,8 @@ class R600OpenCLImageTypeLoweringPass : public ModulePass {
244244
Modified |= replaceSamplerUses(Arg, ResourceID);
245245
}
246246
}
247-
for (unsigned i = 0; i < InstsToErase.size(); ++i) {
248-
InstsToErase[i]->eraseFromParent();
249-
}
247+
for (auto *Inst : InstsToErase)
248+
Inst->eraseFromParent();
250249

251250
return Modified;
252251
}

‎llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -613,10 +613,8 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
613613
TII = ST.getInstrInfo();
614614
MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
615615

616-
for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
617-
BI != BE; ++BI) {
618-
MachineBasicBlock *MBB = &*BI;
619-
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
616+
for (MachineBasicBlock &MBB : MF) {
617+
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
620618
++I) {
621619
MachineInstr &MI = *I;
622620

@@ -665,7 +663,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
665663
Register NewDst = MRI->createVirtualRegister(DestRC);
666664
MachineBasicBlock *BlockToInsertCopy =
667665
MI.isPHI() ? MI.getOperand(MO.getOperandNo() + 1).getMBB()
668-
: MBB;
666+
: &MBB;
669667
MachineBasicBlock::iterator PointToInsertCopy =
670668
MI.isPHI() ? BlockToInsertCopy->getFirstInstrTerminator() : I;
671669

@@ -1095,10 +1093,8 @@ void SIFixSGPRCopies::lowerVGPR2SGPRCopies(MachineFunction &MF) {
10951093

10961094
void SIFixSGPRCopies::fixSCCCopies(MachineFunction &MF) {
10971095
bool IsWave32 = MF.getSubtarget<GCNSubtarget>().isWave32();
1098-
for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
1099-
++BI) {
1100-
MachineBasicBlock *MBB = &*BI;
1101-
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
1096+
for (MachineBasicBlock &MBB : MF) {
1097+
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
11021098
++I) {
11031099
MachineInstr &MI = *I;
11041100
// May already have been lowered.

‎llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1770,8 +1770,7 @@ bool SIFoldOperands::tryFoldRegSequence(MachineInstr &MI) {
17701770
if (!getRegSeqInit(Defs, Reg, MCOI::OPERAND_REGISTER))
17711771
return false;
17721772

1773-
for (auto &Def : Defs) {
1774-
const auto *Op = Def.first;
1773+
for (auto &[Op, SubIdx] : Defs) {
17751774
if (!Op->isReg())
17761775
return false;
17771776
if (TRI->isAGPR(*MRI, Op->getReg()))
@@ -1809,8 +1808,7 @@ bool SIFoldOperands::tryFoldRegSequence(MachineInstr &MI) {
18091808
auto RS = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
18101809
TII->get(AMDGPU::REG_SEQUENCE), Dst);
18111810

1812-
for (unsigned I = 0; I < Defs.size(); ++I) {
1813-
MachineOperand *Def = Defs[I].first;
1811+
for (auto &[Def, SubIdx] : Defs) {
18141812
Def->setIsKill(false);
18151813
if (TRI->isAGPR(*MRI, Def->getReg())) {
18161814
RS.add(*Def);
@@ -1819,7 +1817,7 @@ bool SIFoldOperands::tryFoldRegSequence(MachineInstr &MI) {
18191817
SubDef->getOperand(1).setIsKill(false);
18201818
RS.addReg(SubDef->getOperand(1).getReg(), 0, Def->getSubReg());
18211819
}
1822-
RS.addImm(Defs[I].second);
1820+
RS.addImm(SubIdx);
18231821
}
18241822

18251823
Op->setReg(Dst);

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3250,8 +3250,7 @@ SDValue SITargetLowering::LowerCallResult(
32503250
CCInfo.AnalyzeCallResult(Ins, RetCC);
32513251

32523252
// Copy all of the result registers out of their specified physreg.
3253-
for (unsigned i = 0; i != RVLocs.size(); ++i) {
3254-
CCValAssign VA = RVLocs[i];
3253+
for (CCValAssign VA : RVLocs) {
32553254
SDValue Val;
32563255

32573256
if (VA.isRegLoc()) {
@@ -3642,8 +3641,8 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
36423641

36433642
if (Callee.isUndef() || isNullConstant(Callee)) {
36443643
if (!CLI.IsTailCall) {
3645-
for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
3646-
InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
3644+
for (ISD::InputArg &Arg : CLI.Ins)
3645+
InVals.push_back(DAG.getUNDEF(Arg.VT));
36473646
}
36483647

36493648
return Chain;

‎llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -324,8 +324,7 @@ void SIMachineFunctionInfo::shiftSpillPhysVGPRsToLowestRange(
324324
MachineFunction &MF) {
325325
const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
326326
MachineRegisterInfo &MRI = MF.getRegInfo();
327-
for (unsigned I = 0, E = SpillPhysVGPRs.size(); I < E; ++I) {
328-
Register Reg = SpillPhysVGPRs[I];
327+
for (Register &Reg : SpillPhysVGPRs) {
329328
Register NewReg =
330329
TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
331330
if (!NewReg || NewReg >= Reg)
@@ -334,7 +333,6 @@ void SIMachineFunctionInfo::shiftSpillPhysVGPRsToLowestRange(
334333
MRI.replaceRegWith(Reg, NewReg);
335334

336335
// Update various tables with the new VGPR.
337-
SpillPhysVGPRs[I] = NewReg;
338336
WWMReservedRegs.remove(Reg);
339337
WWMReservedRegs.insert(NewReg);
340338
WWMSpills.insert(std::make_pair(NewReg, WWMSpills[Reg]));
@@ -344,6 +342,8 @@ void SIMachineFunctionInfo::shiftSpillPhysVGPRsToLowestRange(
344342
MBB.removeLiveIn(Reg);
345343
MBB.sortUniqueLiveIns();
346344
}
345+
346+
Reg = NewReg;
347347
}
348348
}
349349

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