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[RISCV] Improve constant materialization by using a sequence that end… (#66943)
…s with 2 addis in some cases. If the lower 13 bits are something like 0x17ff, we can first materialize it as 0x1800 followed by an addi to subtract a small offset. This might be cheaper to materialize since the constant ending in 0x1800 can use a simm12 immediate for its final addi.
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3 files changed

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‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

Lines changed: 19 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -257,10 +257,27 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
257257
assert(ActiveFeatures[RISCV::Feature64Bit] &&
258258
"Expected RV32 to only need 2 instructions");
259259

260+
// If the lower 13 bits are something like 0x17ff, try to add 1 to change the
261+
// lower 13 bits to 0x1800. We can restore this with an ADDI of -1 at the end
262+
// of the sequence. Call generateInstSeqImpl on the new constant which may
263+
// subtract 0xfffffffffffff800 to create another ADDI. This will leave a
264+
// constant with more than 12 trailing zeros for the next recursive step.
265+
if ((Val & 0xfff) != 0 && (Val & 0x1800) == 0x1000) {
266+
int64_t Imm12 = -(0x800 - (Val & 0xfff));
267+
int64_t AdjustedVal = Val - Imm12;
268+
RISCVMatInt::InstSeq TmpSeq;
269+
generateInstSeqImpl(AdjustedVal, ActiveFeatures, TmpSeq);
270+
271+
// Keep the new sequence if it is an improvement.
272+
if ((TmpSeq.size() + 1) < Res.size()) {
273+
TmpSeq.emplace_back(RISCV::ADDI, Imm12);
274+
Res = TmpSeq;
275+
}
276+
}
277+
260278
// If the constant is positive we might be able to generate a shifted constant
261279
// with no leading zeros and use a final SRLI to restore them.
262-
if (Val > 0) {
263-
assert(Res.size() > 2 && "Expected longer sequence");
280+
if (Val > 0 && Res.size() > 2) {
264281
generateInstSeqLeadingZeros(Val, ActiveFeatures, Res);
265282
}
266283

‎llvm/test/CodeGen/RISCV/imm.ll

Lines changed: 33 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -1107,46 +1107,41 @@ define i64 @imm_end_2addi_1() nounwind {
11071107
; RV64I-LABEL: imm_end_2addi_1:
11081108
; RV64I: # %bb.0:
11091109
; RV64I-NEXT: li a0, -2047
1110-
; RV64I-NEXT: slli a0, a0, 27
1110+
; RV64I-NEXT: slli a0, a0, 39
1111+
; RV64I-NEXT: addi a0, a0, -2048
11111112
; RV64I-NEXT: addi a0, a0, -1
1112-
; RV64I-NEXT: slli a0, a0, 12
1113-
; RV64I-NEXT: addi a0, a0, 2047
11141113
; RV64I-NEXT: ret
11151114
;
11161115
; RV64IZBA-LABEL: imm_end_2addi_1:
11171116
; RV64IZBA: # %bb.0:
11181117
; RV64IZBA-NEXT: li a0, -2047
1119-
; RV64IZBA-NEXT: slli a0, a0, 27
1118+
; RV64IZBA-NEXT: slli a0, a0, 39
1119+
; RV64IZBA-NEXT: addi a0, a0, -2048
11201120
; RV64IZBA-NEXT: addi a0, a0, -1
1121-
; RV64IZBA-NEXT: slli a0, a0, 12
1122-
; RV64IZBA-NEXT: addi a0, a0, 2047
11231121
; RV64IZBA-NEXT: ret
11241122
;
11251123
; RV64IZBB-LABEL: imm_end_2addi_1:
11261124
; RV64IZBB: # %bb.0:
11271125
; RV64IZBB-NEXT: li a0, -2047
1128-
; RV64IZBB-NEXT: slli a0, a0, 27
1126+
; RV64IZBB-NEXT: slli a0, a0, 39
1127+
; RV64IZBB-NEXT: addi a0, a0, -2048
11291128
; RV64IZBB-NEXT: addi a0, a0, -1
1130-
; RV64IZBB-NEXT: slli a0, a0, 12
1131-
; RV64IZBB-NEXT: addi a0, a0, 2047
11321129
; RV64IZBB-NEXT: ret
11331130
;
11341131
; RV64IZBS-LABEL: imm_end_2addi_1:
11351132
; RV64IZBS: # %bb.0:
11361133
; RV64IZBS-NEXT: li a0, -2047
1137-
; RV64IZBS-NEXT: slli a0, a0, 27
1134+
; RV64IZBS-NEXT: slli a0, a0, 39
1135+
; RV64IZBS-NEXT: addi a0, a0, -2048
11381136
; RV64IZBS-NEXT: addi a0, a0, -1
1139-
; RV64IZBS-NEXT: slli a0, a0, 12
1140-
; RV64IZBS-NEXT: addi a0, a0, 2047
11411137
; RV64IZBS-NEXT: ret
11421138
;
11431139
; RV64IXTHEADBB-LABEL: imm_end_2addi_1:
11441140
; RV64IXTHEADBB: # %bb.0:
11451141
; RV64IXTHEADBB-NEXT: li a0, -2047
1146-
; RV64IXTHEADBB-NEXT: slli a0, a0, 27
1142+
; RV64IXTHEADBB-NEXT: slli a0, a0, 39
1143+
; RV64IXTHEADBB-NEXT: addi a0, a0, -2048
11471144
; RV64IXTHEADBB-NEXT: addi a0, a0, -1
1148-
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
1149-
; RV64IXTHEADBB-NEXT: addi a0, a0, 2047
11501145
; RV64IXTHEADBB-NEXT: ret
11511146
ret i64 -1125350151030785 ; 0xFFFC_007F_FFFF_F7FF
11521147
}
@@ -2435,21 +2430,14 @@ define i64 @imm_12900925247761() {
24352430
; RV32I-NEXT: addi a1, a1, -1093
24362431
; RV32I-NEXT: ret
24372432
;
2438-
; RV64-NOPOOL-LABEL: imm_12900925247761:
2439-
; RV64-NOPOOL: # %bb.0:
2440-
; RV64-NOPOOL-NEXT: lui a0, 188
2441-
; RV64-NOPOOL-NEXT: addiw a0, a0, -1093
2442-
; RV64-NOPOOL-NEXT: slli a0, a0, 12
2443-
; RV64-NOPOOL-NEXT: addi a0, a0, 273
2444-
; RV64-NOPOOL-NEXT: slli a0, a0, 12
2445-
; RV64-NOPOOL-NEXT: addi a0, a0, 273
2446-
; RV64-NOPOOL-NEXT: ret
2447-
;
2448-
; RV64I-POOL-LABEL: imm_12900925247761:
2449-
; RV64I-POOL: # %bb.0:
2450-
; RV64I-POOL-NEXT: lui a0, %hi(.LCPI52_0)
2451-
; RV64I-POOL-NEXT: ld a0, %lo(.LCPI52_0)(a0)
2452-
; RV64I-POOL-NEXT: ret
2433+
; RV64I-LABEL: imm_12900925247761:
2434+
; RV64I: # %bb.0:
2435+
; RV64I-NEXT: lui a0, 384478
2436+
; RV64I-NEXT: addiw a0, a0, -1911
2437+
; RV64I-NEXT: slli a0, a0, 13
2438+
; RV64I-NEXT: addi a0, a0, -2048
2439+
; RV64I-NEXT: addi a0, a0, -1775
2440+
; RV64I-NEXT: ret
24532441
;
24542442
; RV64IZBA-LABEL: imm_12900925247761:
24552443
; RV64IZBA: # %bb.0:
@@ -2461,32 +2449,29 @@ define i64 @imm_12900925247761() {
24612449
;
24622450
; RV64IZBB-LABEL: imm_12900925247761:
24632451
; RV64IZBB: # %bb.0:
2464-
; RV64IZBB-NEXT: lui a0, 188
2465-
; RV64IZBB-NEXT: addiw a0, a0, -1093
2466-
; RV64IZBB-NEXT: slli a0, a0, 12
2467-
; RV64IZBB-NEXT: addi a0, a0, 273
2468-
; RV64IZBB-NEXT: slli a0, a0, 12
2469-
; RV64IZBB-NEXT: addi a0, a0, 273
2452+
; RV64IZBB-NEXT: lui a0, 384478
2453+
; RV64IZBB-NEXT: addiw a0, a0, -1911
2454+
; RV64IZBB-NEXT: slli a0, a0, 13
2455+
; RV64IZBB-NEXT: addi a0, a0, -2048
2456+
; RV64IZBB-NEXT: addi a0, a0, -1775
24702457
; RV64IZBB-NEXT: ret
24712458
;
24722459
; RV64IZBS-LABEL: imm_12900925247761:
24732460
; RV64IZBS: # %bb.0:
2474-
; RV64IZBS-NEXT: lui a0, 188
2475-
; RV64IZBS-NEXT: addiw a0, a0, -1093
2476-
; RV64IZBS-NEXT: slli a0, a0, 12
2477-
; RV64IZBS-NEXT: addi a0, a0, 273
2478-
; RV64IZBS-NEXT: slli a0, a0, 12
2479-
; RV64IZBS-NEXT: addi a0, a0, 273
2461+
; RV64IZBS-NEXT: lui a0, 384478
2462+
; RV64IZBS-NEXT: addiw a0, a0, -1911
2463+
; RV64IZBS-NEXT: slli a0, a0, 13
2464+
; RV64IZBS-NEXT: addi a0, a0, -2048
2465+
; RV64IZBS-NEXT: addi a0, a0, -1775
24802466
; RV64IZBS-NEXT: ret
24812467
;
24822468
; RV64IXTHEADBB-LABEL: imm_12900925247761:
24832469
; RV64IXTHEADBB: # %bb.0:
2484-
; RV64IXTHEADBB-NEXT: lui a0, 188
2485-
; RV64IXTHEADBB-NEXT: addiw a0, a0, -1093
2486-
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
2487-
; RV64IXTHEADBB-NEXT: addi a0, a0, 273
2488-
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
2489-
; RV64IXTHEADBB-NEXT: addi a0, a0, 273
2470+
; RV64IXTHEADBB-NEXT: lui a0, 384478
2471+
; RV64IXTHEADBB-NEXT: addiw a0, a0, -1911
2472+
; RV64IXTHEADBB-NEXT: slli a0, a0, 13
2473+
; RV64IXTHEADBB-NEXT: addi a0, a0, -2048
2474+
; RV64IXTHEADBB-NEXT: addi a0, a0, -1775
24902475
; RV64IXTHEADBB-NEXT: ret
24912476
ret i64 12900925247761
24922477
}

‎llvm/test/MC/RISCV/rv64i-aliases-valid.s

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -161,15 +161,13 @@ li x9, 0x1000FFFFFFFD
161161
# CHECK-ALIAS-NEXT: not a0, a0
162162
li x10, 0xE000000001FFFFFF
163163
# CHECK-INST: addi a1, zero, -2047
164-
# CHECK-INST-NEXT: slli a1, a1, 27
164+
# CHECK-INST-NEXT: slli a1, a1, 39
165+
# CHECK-INST-NEXT: addi a1, a1, -2048
165166
# CHECK-INST-NEXT: addi a1, a1, -1
166-
# CHECK-INST-NEXT: slli a1, a1, 12
167-
# CHECK-INST-NEXT: addi a1, a1, 2047
168167
# CHECK-ALIAS: li a1, -2047
169-
# CHECK-ALIAS-NEXT: slli a1, a1, 27
168+
# CHECK-ALIAS-NEXT: slli a1, a1, 39
169+
# CHECK-ALIAS-NEXT: addi a1, a1, -2048
170170
# CHECK-ALIAS-NEXT: addi a1, a1, -1
171-
# CHECK-ALIAS-NEXT: slli a1, a1, 12
172-
# CHECK-ALIAS-NEXT: addi a1, a1, 2047
173171
li x11, 0xFFFC007FFFFFF7FF
174172

175173
# CHECK-INST: lui a2, 349525
@@ -398,15 +396,13 @@ lla x9, 0x1000FFFFFFFD
398396
la x10, 0xE000000001FFFFFF
399397
lla x10, 0xE000000001FFFFFF
400398
# CHECK-INST: addi a1, zero, -2047
401-
# CHECK-INST-NEXT: slli a1, a1, 27
399+
# CHECK-INST-NEXT: slli a1, a1, 39
400+
# CHECK-INST-NEXT: addi a1, a1, -2048
402401
# CHECK-INST-NEXT: addi a1, a1, -1
403-
# CHECK-INST-NEXT: slli a1, a1, 12
404-
# CHECK-INST-NEXT: addi a1, a1, 2047
405402
# CHECK-ALIAS: li a1, -2047
406-
# CHECK-ALIAS-NEXT: slli a1, a1, 27
403+
# CHECK-ALIAS-NEXT: slli a1, a1, 39
404+
# CHECK-ALIAS-NEXT: addi a1, a1, -2048
407405
# CHECK-ALIAS-NEXT: addi a1, a1, -1
408-
# CHECK-ALIAS-NEXT: slli a1, a1, 12
409-
# CHECK-ALIAS-NEXT: addi a1, a1, 2047
410406
la x11, 0xFFFC007FFFFFF7FF
411407
lla x11, 0xFFFC007FFFFFF7FF
412408

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