Minor change to a comment.

stefanp-synopsys · stefanp-synopsys · commit c7d3b768795f · 2024-06-14T12:44:38.000-05:00
diff --git a/llvm/test/CodeGen/PowerPC/subreg-lanemasks.mir b/llvm/test/CodeGen/PowerPC/subreg-lanemasks.mir
@@ -5,9 +5,8 @@
 
 # Keep track of all of the lanemasks for various subregsiters.
 #
-# TODO: The mask for %6.sub_vsx1:accrc is the same as the mask for %10.sub_vsx1_then_sub_64:accrc
-#       even though one is a 128 bit register and the other is a 64 bit subregister. This should
-#       be fixed in a later patch.
+# TODO: The mask for %6.sub_vsx1:accrc is the same as the mask for %10.sub_vsx1_then_sub_64:accrc.
+#       Ideally on PowerPC these masks should be different. To be addressed in a later patch.
 #
 # CHECK: %3 [80r,80d:0) 0@80r  L0000000000000004 [80r,80d:0) 0@80r  weight:0.000000e+00
 # CHECK: %4 [96r,96d:0) 0@96r  L0000000000000800 [96r,96d:0) 0@96r  weight:0.000000e+00

Original file line number	Diff line number	Diff line change
`@@ -5,9 +5,8 @@`
`5`	`5`
`6`	`6`	`# Keep track of all of the lanemasks for various subregsiters.`
`7`	`7`	`#`
`8`		`-# TODO: The mask for %6.sub_vsx1:accrc is the same as the mask for %10.sub_vsx1_then_sub_64:accrc`
`9`		`-# even though one is a 128 bit register and the other is a 64 bit subregister. This should`
`10`		`-# be fixed in a later patch.`
	`8`	`+# TODO: The mask for %6.sub_vsx1:accrc is the same as the mask for %10.sub_vsx1_then_sub_64:accrc.`
	`9`	`+# Ideally on PowerPC these masks should be different. To be addressed in a later patch.`
`11`	`10`	`#`
`12`	`11`	`# CHECK: %3 [80r,80d:0) 0@80r L0000000000000004 [80r,80d:0) 0@80r weight:0.000000e+00`
`13`	`12`	`# CHECK: %4 [96r,96d:0) 0@96r L0000000000000800 [96r,96d:0) 0@96r weight:0.000000e+00`