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[RFC][RISCV] Support RISC-V Profiles in -march option
This PR implements the draft riscv-non-isa/riscv-toolchain-conventions#36. Currently, we replace specified profile in `-march` with standard arch string.
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‎clang/test/Driver/riscv-profiles.c

Lines changed: 112 additions & 0 deletions
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@@ -0,0 +1,112 @@
1+
// RUN: %clang -### -c %s 2>&1 -march=rvi20u32 | FileCheck -check-prefix=RVI20U32 %s
2+
// RVI20U32: "-target-cpu" "generic-rv32"
3+
// RVI20U32: "-target-feature" "-a"
4+
// RVI20U32: "-target-feature" "-c"
5+
// RVI20U32: "-target-feature" "-d"
6+
// RVI20U32: "-target-feature" "-f"
7+
// RVI20U32: "-target-feature" "-m"
8+
// RVI20U32: "-target-feature" "+rvi20u32"
9+
// RVI20U32: "-target-abi" "ilp32"
10+
11+
// RUN: %clang -### -c %s 2>&1 -march=rvi20u64 | FileCheck -check-prefix=RVI20U64 %s
12+
// RVI20U64: "-target-cpu" "generic-rv64"
13+
// RVI20U64: "-target-feature" "-a"
14+
// RVI20U64: "-target-feature" "-c"
15+
// RVI20U64: "-target-feature" "-d"
16+
// RVI20U64: "-target-feature" "-f"
17+
// RVI20U64: "-target-feature" "-m"
18+
// RVI20U64: "-target-feature" "+rvi20u64"
19+
// RVI20U64: "-target-abi" "lp64"
20+
21+
// RUN: %clang -### -c %s 2>&1 -march=rva20u64 | FileCheck -check-prefix=RVA20U64 %s
22+
// RVA20U64: "-target-cpu" "generic-rv64"
23+
// RVA20U64: "-target-feature" "+m"
24+
// RVA20U64: "-target-feature" "+a"
25+
// RVA20U64: "-target-feature" "+f"
26+
// RVA20U64: "-target-feature" "+d"
27+
// RVA20U64: "-target-feature" "+c"
28+
// RVA20U64: "-target-feature" "+zicsr"
29+
// RVA20U64: "-target-feature" "+rva20u64"
30+
// RVA20U64: "-target-abi" "lp64d"
31+
32+
// RUN: %clang -### -c %s 2>&1 -march=rva20s64 | FileCheck -check-prefix=RVA20S64 %s
33+
// RVA20S64: "-target-cpu" "generic-rv64"
34+
// RVA20S64: "-target-feature" "+m"
35+
// RVA20S64: "-target-feature" "+a"
36+
// RVA20S64: "-target-feature" "+f"
37+
// RVA20S64: "-target-feature" "+d"
38+
// RVA20S64: "-target-feature" "+c"
39+
// RVA20S64: "-target-feature" "+zicsr"
40+
// RVA20S64: "-target-feature" "+zifencei"
41+
// RVA20S64: "-target-feature" "+rva20s64"
42+
// RVA20S64: "-target-abi" "lp64d"
43+
44+
// RUN: %clang -### -c %s 2>&1 -march=rva22u64 | FileCheck -check-prefix=RVA22U64 %s
45+
// RVA22U64: "-target-cpu" "generic-rv64"
46+
// RVA22U64: "-target-feature" "+m"
47+
// RVA22U64: "-target-feature" "+a"
48+
// RVA22U64: "-target-feature" "+f"
49+
// RVA22U64: "-target-feature" "+d"
50+
// RVA22U64: "-target-feature" "+c"
51+
// RVA22U64: "-target-feature" "+zicbom"
52+
// RVA22U64: "-target-feature" "+zicbop"
53+
// RVA22U64: "-target-feature" "+zicboz"
54+
// RVA22U64: "-target-feature" "+zicsr"
55+
// RVA22U64: "-target-feature" "+zihintpause"
56+
// RVA22U64: "-target-feature" "+zfhmin"
57+
// RVA22U64: "-target-feature" "+zba"
58+
// RVA22U64: "-target-feature" "+zbb"
59+
// RVA22U64: "-target-feature" "+zbs"
60+
// RVA22U64: "-target-feature" "+zkt"
61+
// RVA22U64: "-target-feature" "+rva22u64"
62+
// RVA22U64: "-target-abi" "lp64d"
63+
64+
// RUN: %clang -### -c %s 2>&1 -march=rva22s64 | FileCheck -check-prefix=RVA22S64 %s
65+
// RVA22S64: "-target-cpu" "generic-rv64"
66+
// RVA22S64: "-target-feature" "+m"
67+
// RVA22S64: "-target-feature" "+a"
68+
// RVA22S64: "-target-feature" "+f"
69+
// RVA22S64: "-target-feature" "+d"
70+
// RVA22S64: "-target-feature" "+c"
71+
// RVA22S64: "-target-feature" "+zicbom"
72+
// RVA22S64: "-target-feature" "+zicbop"
73+
// RVA22S64: "-target-feature" "+zicboz"
74+
// RVA22S64: "-target-feature" "+zicsr"
75+
// RVA22S64: "-target-feature" "+zifencei"
76+
// RVA22S64: "-target-feature" "+zihintpause"
77+
// RVA22S64: "-target-feature" "+zfhmin"
78+
// RVA22S64: "-target-feature" "+zba"
79+
// RVA22S64: "-target-feature" "+zbb"
80+
// RVA22S64: "-target-feature" "+zbs"
81+
// RVA22S64: "-target-feature" "+zkt"
82+
// RVA22S64: "-target-feature" "+svinval"
83+
// RVA22S64: "-target-feature" "+svpbmt"
84+
// RVA22S64: "-target-feature" "+rva22s64"
85+
// RVA22S64: "-target-abi" "lp64d"
86+
87+
// RUN: %clang -### -c %s 2>&1 -march=rva22u64_zfa | FileCheck -check-prefix=PROFILE-WITH-ADDITIONAL %s
88+
// PROFILE-WITH-ADDITIONAL: "-target-cpu" "generic-rv64"
89+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+m"
90+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+a"
91+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+f"
92+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+d"
93+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+c"
94+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zicbom"
95+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zicbop"
96+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zicboz"
97+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zicsr"
98+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zihintpause"
99+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zfa"
100+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zfhmin"
101+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zba"
102+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zbb"
103+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zbs"
104+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zkt"
105+
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+rva22u64"
106+
// PROFILE-WITH-ADDITIONAL: "-target-abi" "lp64d"
107+
108+
// RUN: not %clang -### -c %s 2>&1 -march=rva19u64_zfa | FileCheck -check-prefix=INVALID-PROFILE %s
109+
// INVALID-PROFILE: error: invalid arch name 'rva19u64_zfa', unsupported profile
110+
111+
// RUN: not %clang -### -c %s 2>&1 -march=rva22u64zfa | FileCheck -check-prefix=INVALID-ADDITIONAL %s
112+
// INVALID-ADDITIONAL: error: invalid arch name 'rva22u64zfa', additional extensions must be after separator '_'

‎llvm/include/llvm/Support/RISCVISAInfo.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,7 @@ class RISCVISAInfo {
8080
unsigned getMaxVLen() const { return 65536; }
8181
unsigned getMaxELen() const { return MaxELen; }
8282
unsigned getMaxELenFp() const { return MaxELenFp; }
83+
std::string getProfile() const { return Profile; }
8384

8485
bool hasExtension(StringRef Ext) const;
8586
std::string toString() const;
@@ -96,12 +97,13 @@ class RISCVISAInfo {
9697

9798
private:
9899
RISCVISAInfo(unsigned XLen)
99-
: XLen(XLen), FLen(0), MinVLen(0), MaxELen(0), MaxELenFp(0) {}
100+
: XLen(XLen), FLen(0), MinVLen(0), MaxELen(0), MaxELenFp(0), Profile() {}
100101

101102
unsigned XLen;
102103
unsigned FLen;
103104
unsigned MinVLen;
104105
unsigned MaxELen, MaxELenFp;
106+
std::string Profile;
105107

106108
OrderedExtensionMap Exts;
107109

‎llvm/lib/Support/RISCVISAInfo.cpp

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,11 @@ struct RISCVSupportedExtension {
3636
}
3737
};
3838

39+
struct RISCVProfile {
40+
const char *Name;
41+
const char *MArch;
42+
};
43+
3944
} // end anonymous namespace
4045

4146
static constexpr StringLiteral AllStdExts = "mafdqlcbkjtpvnh";
@@ -240,6 +245,17 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
240245
};
241246
// clang-format on
242247

248+
static const RISCVProfile SupportedProfiles[] = {
249+
{"rvi20u32", "rv32i"},
250+
{"rvi20u64", "rv64i"},
251+
{"rva20u64", "rv64imafdc_zicsr"},
252+
{"rva20s64", "rv64imafdc_zicsr_zifencei"},
253+
{"rva22u64", "rv64imafdc_zicsr_zihintpause_zba_zbb_zbs_zicbom_zicbop_"
254+
"zicboz_zfhmin_zkt"},
255+
{"rva22s64", "rv64imafdc_zicsr_zifencei_zihintpause_zba_zbb_zbs_zicbom_"
256+
"zicbop_zicboz_zfhmin_zkt_svpbmt_svinval"},
257+
};
258+
243259
static void verifyTables() {
244260
#ifndef NDEBUG
245261
static std::atomic<bool> TableChecked(false);
@@ -527,6 +543,11 @@ std::vector<std::string> RISCVISAInfo::toFeatures(bool AddAllExtensions,
527543
Features.push_back((llvm::Twine("-experimental-") + Ext.Name).str());
528544
}
529545
}
546+
547+
// Add profile feature.
548+
if (!Profile.empty())
549+
Features.push_back((Twine("+") + Profile).str());
550+
530551
return Features;
531552
}
532553

@@ -839,6 +860,36 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
839860
"string must be lowercase");
840861
}
841862

863+
bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
864+
Arch.starts_with("rvb") || Arch.starts_with("rvm");
865+
std::string NewArch;
866+
std::string ProfileName;
867+
if (IsProfile) {
868+
const RISCVProfile *FoundProfile = nullptr;
869+
for (const RISCVProfile &Profile : SupportedProfiles) {
870+
if (Arch.starts_with(Profile.Name)) {
871+
FoundProfile = &Profile;
872+
break;
873+
}
874+
}
875+
876+
if (!FoundProfile)
877+
return createStringError(errc::invalid_argument, "unsupported profile");
878+
879+
ProfileName = FoundProfile->Name;
880+
NewArch = FoundProfile->MArch;
881+
882+
StringRef ArchWithoutProfile = Arch.substr(ProfileName.size());
883+
if (!ArchWithoutProfile.empty()) {
884+
if (!ArchWithoutProfile.starts_with("_"))
885+
return createStringError(
886+
errc::invalid_argument,
887+
"additional extensions must be after separator '_'");
888+
NewArch = NewArch + ArchWithoutProfile.str();
889+
}
890+
Arch = NewArch;
891+
}
892+
842893
bool HasRV64 = Arch.starts_with("rv64");
843894
// ISA string must begin with rv32 or rv64.
844895
if (!(Arch.starts_with("rv32") || HasRV64) || (Arch.size() < 5)) {
@@ -849,6 +900,9 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
849900

850901
unsigned XLen = HasRV64 ? 64 : 32;
851902
std::unique_ptr<RISCVISAInfo> ISAInfo(new RISCVISAInfo(XLen));
903+
if (!ProfileName.empty())
904+
ISAInfo->Profile = ProfileName;
905+
852906
MapVector<std::string, RISCVISAInfo::ExtensionVersion,
853907
std::map<std::string, unsigned>>
854908
SeenExtMap;

‎llvm/lib/Target/RISCV/RISCV.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,12 @@ include "RISCVSchedXiangShanNanHu.td"
5252

5353
include "RISCVProcessors.td"
5454

55+
//===----------------------------------------------------------------------===//
56+
// RISC-V profiles supported.
57+
//===----------------------------------------------------------------------===//
58+
59+
include "RISCVProfiles.td"
60+
5561
//===----------------------------------------------------------------------===//
5662
// Define the RISC-V target.
5763
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVProfiles.td

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,70 @@
1+
//===------ RISCVProfiles.td - RISC-V Profiles -------------*- tablegen -*-===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
9+
class RISCVProfile<string name, list<SubtargetFeature> features>
10+
: SubtargetFeature<name, "RISCVProfile", NAME,
11+
"RISC-V " # name # " profile",
12+
features>;
13+
14+
def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit]>;
15+
16+
def RVI20U64 : RISCVProfile<"rvi20u64", [Feature64Bit]>;
17+
18+
def RVA20U64 : RISCVProfile<"rva20u64", [Feature64Bit,
19+
FeatureStdExtM,
20+
FeatureStdExtA,
21+
FeatureStdExtF,
22+
FeatureStdExtD,
23+
FeatureStdExtC,
24+
FeatureStdExtZicsr]>;
25+
26+
def RVA20S64 : RISCVProfile<"rva20s64", [Feature64Bit,
27+
FeatureStdExtM,
28+
FeatureStdExtA,
29+
FeatureStdExtF,
30+
FeatureStdExtD,
31+
FeatureStdExtC,
32+
FeatureStdExtZicsr,
33+
FeatureStdExtZifencei]>;
34+
35+
def RVA22U64 : RISCVProfile<"rva22u64", [Feature64Bit,
36+
FeatureStdExtM,
37+
FeatureStdExtA,
38+
FeatureStdExtF,
39+
FeatureStdExtD,
40+
FeatureStdExtC,
41+
FeatureStdExtZba,
42+
FeatureStdExtZbb,
43+
FeatureStdExtZbs,
44+
FeatureStdExtZfhmin,
45+
FeatureStdExtZicbom,
46+
FeatureStdExtZicbop,
47+
FeatureStdExtZicboz,
48+
FeatureStdExtZkt,
49+
FeatureStdExtZicsr,
50+
FeatureStdExtZihintpause]>;
51+
52+
def RVA22S64 : RISCVProfile<"rva22s64", [Feature64Bit,
53+
FeatureStdExtM,
54+
FeatureStdExtA,
55+
FeatureStdExtF,
56+
FeatureStdExtD,
57+
FeatureStdExtC,
58+
FeatureStdExtZba,
59+
FeatureStdExtZbb,
60+
FeatureStdExtZbs,
61+
FeatureStdExtZfhmin,
62+
FeatureStdExtZicbom,
63+
FeatureStdExtZicbop,
64+
FeatureStdExtZicboz,
65+
FeatureStdExtZkt,
66+
FeatureStdExtZicsr,
67+
FeatureStdExtZifencei,
68+
FeatureStdExtZihintpause,
69+
FeatureStdExtSvpbmt,
70+
FeatureStdExtSvinval]>;

‎llvm/lib/Target/RISCV/RISCVSubtarget.h

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,16 @@ struct RISCVTuneInfo {
5656
#include "RISCVGenSearchableTables.inc"
5757
} // namespace RISCVTuneInfoTable
5858

59+
enum RISCVProfileEnum : uint8_t {
60+
Unspecified,
61+
RVA20S64,
62+
RVA20U64,
63+
RVA22S64,
64+
RVA22U64,
65+
RVI20U32,
66+
RVI20U64,
67+
};
68+
5969
class RISCVSubtarget : public RISCVGenSubtargetInfo {
6070
public:
6171
// clang-format off
@@ -70,6 +80,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
7080

7181
RISCVProcFamilyEnum RISCVProcFamily = Others;
7282

83+
RISCVProfileEnum RISCVProfile = Unspecified;
84+
7385
#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
7486
bool ATTRIBUTE = DEFAULT;
7587
#include "RISCVGenSubtargetInfo.inc"
@@ -138,6 +150,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
138150
/// initializeProperties().
139151
RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
140152

153+
RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; }
154+
141155
#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
142156
bool GETTER() const { return ATTRIBUTE; }
143157
#include "RISCVGenSubtargetInfo.inc"

‎llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -252,6 +252,14 @@
252252
; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
253253
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
254254

255+
; Tests for profile features.
256+
; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s
257+
; RUN: llc -mtriple=riscv64 -mattr=+rvi20u64 %s -o - | FileCheck --check-prefix=RVI20U64 %s
258+
; RUN: llc -mtriple=riscv64 -mattr=+rva20u64 %s -o - | FileCheck --check-prefix=RVA20U64 %s
259+
; RUN: llc -mtriple=riscv64 -mattr=+rva20s64 %s -o - | FileCheck --check-prefix=RVA20S64 %s
260+
; RUN: llc -mtriple=riscv64 -mattr=+rva22u64 %s -o - | FileCheck --check-prefix=RVA22U64 %s
261+
; RUN: llc -mtriple=riscv64 -mattr=+rva22s64 %s -o - | FileCheck --check-prefix=RVA22S64 %s
262+
255263
; CHECK: .attribute 4, 16
256264

257265
; RV32M: .attribute 5, "rv32i2p1_m2p0"
@@ -504,6 +512,13 @@
504512
; RV64SUPM: .attribute 5, "rv64i2p1_supm0p8"
505513
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
506514

515+
; RVI20U32: .attribute 5, "rv32i2p1"
516+
; RVI20U64: .attribute 5, "rv64i2p1"
517+
; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
518+
; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0"
519+
; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicbom1p0_zicbop1p0_zicboz1p0_zicsr2p0_zihintpause2p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
520+
; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicbom1p0_zicbop1p0_zicboz1p0_zicsr2p0_zifencei2p0_zihintpause2p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_svinval1p0_svpbmt1p0"
521+
507522
define i32 @addi(i32 %a) {
508523
%1 = add i32 %a, 1
509524
ret i32 %1

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