@@ -118,6 +118,10 @@ def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
118
118
def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
119
119
SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
120
120
]>;
121
+ def SDTIntShiftPairOp : SDTypeProfile<2, 3, [ // shl_parts, sra_parts, srl_parts
122
+ SDTCisInt<0>, SDTCisSameAs<1, 0>,
123
+ SDTCisSameAs<2, 0>, SDTCisSameAs<3, 0>, SDTCisInt<4>
124
+ ]>;
121
125
def SDTIntShiftDOp: SDTypeProfile<1, 3, [ // fshl, fshr
122
126
SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
123
127
]>;
@@ -422,6 +426,9 @@ def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
422
426
def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
423
427
def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
424
428
def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
429
+ def shl_parts : SDNode<"ISD::SHL_PARTS" , SDTIntShiftPairOp>;
430
+ def sra_parts : SDNode<"ISD::SRA_PARTS" , SDTIntShiftPairOp>;
431
+ def srl_parts : SDNode<"ISD::SRL_PARTS" , SDTIntShiftPairOp>;
425
432
def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>;
426
433
def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>;
427
434
def and : SDNode<"ISD::AND" , SDTIntBinOp,
0 commit comments