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Remove strict converts
1 parent ae438d1 commit c87775c

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3 files changed

+13
-46
lines changed

3 files changed

+13
-46
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 8 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1454,12 +1454,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
14541454
setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
14551455
setOperationAction(ISD::UINT_TO_FP, VT, Custom);
14561456
setOperationAction(ISD::SINT_TO_FP, VT, Custom);
1457-
setOperationAction(ISD::STRICT_UINT_TO_FP, VT, Custom);
1458-
setOperationAction(ISD::STRICT_SINT_TO_FP, VT, Custom);
14591457
setOperationAction(ISD::FP_TO_UINT, VT, Custom);
14601458
setOperationAction(ISD::FP_TO_SINT, VT, Custom);
1461-
setOperationAction(ISD::STRICT_FP_TO_UINT, VT, Custom);
1462-
setOperationAction(ISD::STRICT_FP_TO_SINT, VT, Custom);
14631459
setOperationAction(ISD::MLOAD, VT, Custom);
14641460
setOperationAction(ISD::MUL, VT, Custom);
14651461
setOperationAction(ISD::MULHS, VT, Custom);
@@ -2142,8 +2138,6 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
21422138
setOperationAction(ISD::FP_ROUND, VT, Default);
21432139
setOperationAction(ISD::FP_TO_SINT, VT, Default);
21442140
setOperationAction(ISD::FP_TO_UINT, VT, Default);
2145-
setOperationAction(ISD::STRICT_FP_TO_SINT, VT, Default);
2146-
setOperationAction(ISD::STRICT_FP_TO_UINT, VT, Default);
21472141
setOperationAction(ISD::FRINT, VT, Default);
21482142
setOperationAction(ISD::LRINT, VT, Default);
21492143
setOperationAction(ISD::LLRINT, VT, Default);
@@ -2170,7 +2164,6 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
21702164
setOperationAction(ISD::SIGN_EXTEND, VT, Default);
21712165
setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Default);
21722166
setOperationAction(ISD::SINT_TO_FP, VT, Default);
2173-
setOperationAction(ISD::STRICT_SINT_TO_FP, VT, Default);
21742167
setOperationAction(ISD::SMAX, VT, Default);
21752168
setOperationAction(ISD::SMIN, VT, Default);
21762169
setOperationAction(ISD::SPLAT_VECTOR, VT, Default);
@@ -2181,7 +2174,6 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
21812174
setOperationAction(ISD::TRUNCATE, VT, Default);
21822175
setOperationAction(ISD::UDIV, VT, Default);
21832176
setOperationAction(ISD::UINT_TO_FP, VT, Default);
2184-
setOperationAction(ISD::STRICT_UINT_TO_FP, VT, Default);
21852177
setOperationAction(ISD::UMAX, VT, Default);
21862178
setOperationAction(ISD::UMIN, VT, Default);
21872179
setOperationAction(ISD::VECREDUCE_ADD, VT, Default);
@@ -4649,8 +4641,8 @@ static bool CanLowerToScalarSVEFPIntConversion(EVT VT) {
46494641

46504642
/// Lowers a scalar FP conversion (to/from) int to SVE.
46514643
static SDValue LowerScalarFPConversionToSVE(SDValue Op, SelectionDAG &DAG) {
4652-
bool IsStrict = Op->isStrictFPOpcode();
4653-
SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
4644+
assert(!Op->isStrictFPOpcode() && "strict fp ops not supported");
4645+
SDValue SrcVal = Op.getOperand(0);
46544646
EVT SrcTy = SrcVal.getValueType();
46554647
EVT DestTy = Op.getValueType();
46564648
EVT SrcVecTy;
@@ -4672,14 +4664,9 @@ static SDValue LowerScalarFPConversionToSVE(SDValue Op, SelectionDAG &DAG) {
46724664
SDValue ZeroIdx = DAG.getVectorIdxConstant(0, dl);
46734665
SDValue Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SrcVecTy,
46744666
DAG.getUNDEF(SrcVecTy), SrcVal, ZeroIdx);
4675-
Vec = IsStrict ? DAG.getNode(Op.getOpcode(), dl, {DestVecTy, MVT::Other},
4676-
{Op.getOperand(0), Vec})
4677-
: DAG.getNode(Op.getOpcode(), dl, DestVecTy, Vec);
4678-
SDValue Scalar =
4679-
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, ZeroIdx);
4680-
if (IsStrict)
4681-
return DAG.getMergeValues({Scalar, Vec.getValue(1)}, dl);
4682-
return Scalar;
4667+
Vec = DAG.getNode(Op.getOpcode(), dl, DestVecTy, Vec);
4668+
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
4669+
ZeroIdx);
46834670
}
46844671

46854672
SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
@@ -4690,7 +4677,7 @@ SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
46904677
if (SrcVal.getValueType().isVector())
46914678
return LowerVectorFP_TO_INT(Op, DAG);
46924679

4693-
if (!Subtarget->isNeonAvailable() &&
4680+
if (!IsStrict && !Subtarget->isNeonAvailable() &&
46944681
Subtarget->isSVEorStreamingSVEAvailable() &&
46954682
CanLowerToScalarSVEFPIntConversion(SrcVal.getValueType()) &&
46964683
CanLowerToScalarSVEFPIntConversion(Op.getValueType()))
@@ -4999,7 +4986,7 @@ SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
49994986
bool IsStrict = Op->isStrictFPOpcode();
50004987
SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
50014988

5002-
if (!Subtarget->isNeonAvailable() &&
4989+
if (!IsStrict && !Subtarget->isNeonAvailable() &&
50034990
Subtarget->isSVEorStreamingSVEAvailable() &&
50044991
CanLowerToScalarSVEFPIntConversion(SrcVal.getValueType()) &&
50054992
CanLowerToScalarSVEFPIntConversion(Op.getValueType()))
@@ -28411,12 +28398,7 @@ SDValue AArch64TargetLowering::LowerToPredicatedOp(SDValue Op,
2841128398
assert(VT.isScalableVector() && "Only expect to lower scalable vector op!");
2841228399

2841328400
SmallVector<SDValue, 4> Operands = {Pg};
28414-
SDValue Chain{};
2841528401
for (const SDValue &V : Op->op_values()) {
28416-
if (!isa<CondCodeSDNode>(V) && V.getValueType() == MVT::Other) {
28417-
Chain = V;
28418-
continue;
28419-
}
2842028402
assert((!V.getValueType().isVector() ||
2842128403
V.getValueType().isScalableVector()) &&
2842228404
"Only scalable vectors are supported!");
@@ -28426,10 +28408,7 @@ SDValue AArch64TargetLowering::LowerToPredicatedOp(SDValue Op,
2842628408
if (isMergePassthruOpcode(NewOp))
2842728409
Operands.push_back(DAG.getUNDEF(VT));
2842828410

28429-
auto NewNode = DAG.getNode(NewOp, DL, VT, Operands, Op->getFlags());
28430-
if (Chain)
28431-
return DAG.getMergeValues({NewNode, Chain}, DL);
28432-
return NewNode;
28411+
return DAG.getNode(NewOp, DL, VT, Operands, Op->getFlags());
2843328412
}
2843428413

2843528414
// If a fixed length vector operation has no side effects when applied to

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-to-int.ll

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -228,10 +228,7 @@ define i64 @f64_to_u64(double %x) {
228228
define i32 @strict_convert_signed(double %x) {
229229
; CHECK-LABEL: strict_convert_signed:
230230
; CHECK: // %bb.0: // %entry
231-
; CHECK-NEXT: ptrue p0.d
232-
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
233-
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.d
234-
; CHECK-NEXT: fmov w0, s0
231+
; CHECK-NEXT: fcvtzs w0, d0
235232
; CHECK-NEXT: ret
236233
;
237234
; NONEON-NOSVE-LABEL: strict_convert_signed:
@@ -246,10 +243,7 @@ define i32 @strict_convert_signed(double %x) {
246243
define i32 @strict_convert_unsigned(float %x) {
247244
; CHECK-LABEL: strict_convert_unsigned:
248245
; CHECK: // %bb.0: // %entry
249-
; CHECK-NEXT: ptrue p0.s
250-
; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0
251-
; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
252-
; CHECK-NEXT: fmov w0, s0
246+
; CHECK-NEXT: fcvtzu w0, s0
253247
; CHECK-NEXT: ret
254248
;
255249
; NONEON-NOSVE-LABEL: strict_convert_unsigned:

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-int-to-fp.ll

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s
3-
; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s
3+
; RUN: llc -mattr=+sve,+sme -force-streaming < %s | FileCheck %s
44
; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE
55

66
target triple = "aarch64-unknown-linux-gnu"
@@ -228,10 +228,7 @@ entry:
228228
define half @strict_convert_signed(i32 %x) {
229229
; CHECK-LABEL: strict_convert_signed:
230230
; CHECK: // %bb.0: // %entry
231-
; CHECK-NEXT: fmov s0, w0
232-
; CHECK-NEXT: ptrue p0.s
233-
; CHECK-NEXT: scvtf z0.h, p0/m, z0.s
234-
; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0
231+
; CHECK-NEXT: scvtf h0, w0
235232
; CHECK-NEXT: ret
236233
;
237234
; NONEON-NOSVE-LABEL: strict_convert_signed:
@@ -247,10 +244,7 @@ entry:
247244
define float @strict_convert_unsigned(i64 %x) {
248245
; CHECK-LABEL: strict_convert_unsigned:
249246
; CHECK: // %bb.0: // %entry
250-
; CHECK-NEXT: fmov d0, x0
251-
; CHECK-NEXT: ptrue p0.d
252-
; CHECK-NEXT: ucvtf z0.s, p0/m, z0.d
253-
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0
247+
; CHECK-NEXT: ucvtf s0, x0
254248
; CHECK-NEXT: ret
255249
;
256250
; NONEON-NOSVE-LABEL: strict_convert_unsigned:

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