[RISCV] Add LD_RV32/SD_RV32 to RISCVInstrInfo::canFoldIntoAddrMode.

Author: topperc

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -2935,6 +2935,7 @@ bool RISCVInstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
   case RISCV::LW_INX:
   case RISCV::LWU:
   case RISCV::LD:
+  case RISCV::LD_RV32:
   case RISCV::FLH:
   case RISCV::FLW:
   case RISCV::FLD:
@@ -2944,6 +2945,7 @@ bool RISCVInstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
   case RISCV::SW:
   case RISCV::SW_INX:
   case RISCV::SD:
+  case RISCV::SD_RV32:
   case RISCV::FSH:
   case RISCV::FSW:
   case RISCV::FSD:

llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll

@@ -61,14 +61,13 @@ define double @fold_addi_from_different_bb(i64 %k, i64 %n, ptr %a) nounwind {
 ; CHECK-NEXT:    li s3, 0
 ; CHECK-NEXT:    li s6, 0
 ; CHECK-NEXT:    slli a0, a0, 4
-; CHECK-NEXT:    add a0, s0, a0
-; CHECK-NEXT:    addi s7, a0, 8
+; CHECK-NEXT:    add s7, s0, a0
 ; CHECK-NEXT:    fcvt.d.w s4, zero
 ; CHECK-NEXT:  .LBB2_5: # %for.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    mv a0, s0
 ; CHECK-NEXT:    call f
-; CHECK-NEXT:    ld a0, 0(s7)
+; CHECK-NEXT:    ld a0, 8(s7)
 ; CHECK-NEXT:    addi s3, s3, 1
 ; CHECK-NEXT:    seqz a2, s3
 ; CHECK-NEXT:    add s6, s6, a2
@@ -122,11 +121,10 @@ define void @split_offset(ptr %dest, double %x) {
 ; CHECK-NEXT:    mv a3, a2
 ; CHECK-NEXT:    addi a0, a0, 2047
 ; CHECK-NEXT:    mv a2, a1
-; CHECK-NEXT:    addi a1, a0, 1
 ; CHECK-NEXT:    sd a2, 1(a0)
-; CHECK-NEXT:    sd a2, 8(a1)
-; CHECK-NEXT:    sd a2, 16(a1)
-; CHECK-NEXT:    sd a2, 24(a1)
+; CHECK-NEXT:    sd a2, 9(a0)
+; CHECK-NEXT:    sd a2, 17(a0)
+; CHECK-NEXT:    sd a2, 25(a0)
 ; CHECK-NEXT:    ret
   %p1 = getelementptr double, ptr %dest, i32 256
   store double %x, ptr %p1