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true16 for v_sin_f16
1 parent 46e7823 commit c880b44

28 files changed

+1030
-462
lines changed

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1045,7 +1045,7 @@ defm V_CEIL_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05c, "v_ceil_f16
10451045
defm V_TRUNC_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05d, "v_trunc_f16">;
10461046
defm V_RNDNE_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05e, "v_rndne_f16">;
10471047
defm V_FRACT_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05f, "v_fract_f16">;
1048-
defm V_SIN_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x060, "v_sin_f16">;
1048+
defm V_SIN_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x060, "v_sin_f16">;
10491049
defm V_COS_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x061, "v_cos_f16">;
10501050
defm V_SAT_PK_U8_I16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x062, "v_sat_pk_u8_i16">;
10511051
defm V_CVT_NORM_I16_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x063, "v_cvt_norm_i16_f16">;

‎llvm/test/MC/AMDGPU/gfx11_asm_vop1.s

Lines changed: 45 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -3281,50 +3281,65 @@ v_sat_pk_u8_i16 v5, src_scc
32813281
v_sat_pk_u8_i16 v127, 0xfe0b
32823282
// GFX11: v_sat_pk_u8_i16_e32 v127, 0xfe0b ; encoding: [0xff,0xc4,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
32833283

3284-
v_sin_f16 v5, v1
3285-
// GFX11: v_sin_f16_e32 v5, v1 ; encoding: [0x01,0xc1,0x0a,0x7e]
3284+
v_sin_f16 v5.l, v1.l
3285+
// GFX11: v_sin_f16_e32 v5.l, v1.l ; encoding: [0x01,0xc1,0x0a,0x7e]
32863286

3287-
v_sin_f16 v5, v127
3288-
// GFX11: v_sin_f16_e32 v5, v127 ; encoding: [0x7f,0xc1,0x0a,0x7e]
3287+
v_sin_f16 v5.l, v127.l
3288+
// GFX11: v_sin_f16_e32 v5.l, v127.l ; encoding: [0x7f,0xc1,0x0a,0x7e]
32893289

3290-
v_sin_f16 v5, s1
3291-
// GFX11: v_sin_f16_e32 v5, s1 ; encoding: [0x01,0xc0,0x0a,0x7e]
3290+
v_sin_f16 v5.l, s1
3291+
// GFX11: v_sin_f16_e32 v5.l, s1 ; encoding: [0x01,0xc0,0x0a,0x7e]
32923292

3293-
v_sin_f16 v5, s105
3294-
// GFX11: v_sin_f16_e32 v5, s105 ; encoding: [0x69,0xc0,0x0a,0x7e]
3293+
v_sin_f16 v5.l, s105
3294+
// GFX11: v_sin_f16_e32 v5.l, s105 ; encoding: [0x69,0xc0,0x0a,0x7e]
32953295

3296-
v_sin_f16 v5, vcc_lo
3297-
// GFX11: v_sin_f16_e32 v5, vcc_lo ; encoding: [0x6a,0xc0,0x0a,0x7e]
3296+
v_sin_f16 v5.l, vcc_lo
3297+
// GFX11: v_sin_f16_e32 v5.l, vcc_lo ; encoding: [0x6a,0xc0,0x0a,0x7e]
32983298

3299-
v_sin_f16 v5, vcc_hi
3300-
// GFX11: v_sin_f16_e32 v5, vcc_hi ; encoding: [0x6b,0xc0,0x0a,0x7e]
3299+
v_sin_f16 v5.l, vcc_hi
3300+
// GFX11: v_sin_f16_e32 v5.l, vcc_hi ; encoding: [0x6b,0xc0,0x0a,0x7e]
33013301

3302-
v_sin_f16 v5, ttmp15
3303-
// GFX11: v_sin_f16_e32 v5, ttmp15 ; encoding: [0x7b,0xc0,0x0a,0x7e]
3302+
v_sin_f16 v5.l, ttmp15
3303+
// GFX11: v_sin_f16_e32 v5.l, ttmp15 ; encoding: [0x7b,0xc0,0x0a,0x7e]
33043304

3305-
v_sin_f16 v5, m0
3306-
// GFX11: v_sin_f16_e32 v5, m0 ; encoding: [0x7d,0xc0,0x0a,0x7e]
3305+
v_sin_f16 v5.l, m0
3306+
// GFX11: v_sin_f16_e32 v5.l, m0 ; encoding: [0x7d,0xc0,0x0a,0x7e]
33073307

3308-
v_sin_f16 v5, exec_lo
3309-
// GFX11: v_sin_f16_e32 v5, exec_lo ; encoding: [0x7e,0xc0,0x0a,0x7e]
3308+
v_sin_f16 v5.l, exec_lo
3309+
// GFX11: v_sin_f16_e32 v5.l, exec_lo ; encoding: [0x7e,0xc0,0x0a,0x7e]
33103310

3311-
v_sin_f16 v5, exec_hi
3312-
// GFX11: v_sin_f16_e32 v5, exec_hi ; encoding: [0x7f,0xc0,0x0a,0x7e]
3311+
v_sin_f16 v5.l, exec_hi
3312+
// GFX11: v_sin_f16_e32 v5.l, exec_hi ; encoding: [0x7f,0xc0,0x0a,0x7e]
33133313

3314-
v_sin_f16 v5, null
3315-
// GFX11: v_sin_f16_e32 v5, null ; encoding: [0x7c,0xc0,0x0a,0x7e]
3314+
v_sin_f16 v5.l, null
3315+
// GFX11: v_sin_f16_e32 v5.l, null ; encoding: [0x7c,0xc0,0x0a,0x7e]
33163316

3317-
v_sin_f16 v5, -1
3318-
// GFX11: v_sin_f16_e32 v5, -1 ; encoding: [0xc1,0xc0,0x0a,0x7e]
3317+
v_sin_f16 v5.l, -1
3318+
// GFX11: v_sin_f16_e32 v5.l, -1 ; encoding: [0xc1,0xc0,0x0a,0x7e]
33193319

3320-
v_sin_f16 v5, 0.5
3321-
// GFX11: v_sin_f16_e32 v5, 0.5 ; encoding: [0xf0,0xc0,0x0a,0x7e]
3320+
v_sin_f16 v5.l, 0.5
3321+
// GFX11: v_sin_f16_e32 v5.l, 0.5 ; encoding: [0xf0,0xc0,0x0a,0x7e]
33223322

3323-
v_sin_f16 v5, src_scc
3324-
// GFX11: v_sin_f16_e32 v5, src_scc ; encoding: [0xfd,0xc0,0x0a,0x7e]
3323+
v_sin_f16 v5.l, src_scc
3324+
// GFX11: v_sin_f16_e32 v5.l, src_scc ; encoding: [0xfd,0xc0,0x0a,0x7e]
33253325

3326-
v_sin_f16 v127, 0xfe0b
3327-
// GFX11: v_sin_f16_e32 v127, 0xfe0b ; encoding: [0xff,0xc0,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
3326+
v_sin_f16 v127.l, 0xfe0b
3327+
// GFX11: v_sin_f16_e32 v127.l, 0xfe0b ; encoding: [0xff,0xc0,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
3328+
3329+
v_sin_f16 v5.l, v1.h
3330+
// GFX11: v_sin_f16_e32 v5.l, v1.h ; encoding: [0x81,0xc1,0x0a,0x7e]
3331+
3332+
v_sin_f16 v5.l, v127.h
3333+
// GFX11: v_sin_f16_e32 v5.l, v127.h ; encoding: [0xff,0xc1,0x0a,0x7e]
3334+
3335+
v_sin_f16 v127.l, 0.5
3336+
// GFX11: v_sin_f16_e32 v127.l, 0.5 ; encoding: [0xf0,0xc0,0xfe,0x7e]
3337+
3338+
v_sin_f16 v5.h, src_scc
3339+
// GFX11: v_sin_f16_e32 v5.h, src_scc ; encoding: [0xfd,0xc0,0x0a,0x7f]
3340+
3341+
v_sin_f16 v127.h, 0xfe0b
3342+
// GFX11: v_sin_f16_e32 v127.h, 0xfe0b ; encoding: [0xff,0xc0,0xfe,0x7f,0x0b,0xfe,0x00,0x00]
33283343

33293344
v_sin_f32 v5, v1
33303345
// GFX11: v_sin_f32_e32 v5, v1 ; encoding: [0x01,0x6b,0x0a,0x7e]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s

Lines changed: 37 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -2564,47 +2564,56 @@ v_sat_pk_u8_i16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
25642564
v_sat_pk_u8_i16 v127, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
25652565
// GFX11: v_sat_pk_u8_i16_dpp v127, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xc4,0xfe,0x7e,0xff,0x6f,0x05,0x30]
25662566

2567-
v_sin_f16 v5, v1 quad_perm:[3,2,1,0]
2568-
// GFX11: v_sin_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1b,0x00,0xff]
2567+
v_sin_f16 v5.l, v1.l quad_perm:[3,2,1,0]
2568+
// GFX11: v_sin_f16_dpp v5.l, v1.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1b,0x00,0xff]
25692569

2570-
v_sin_f16 v5, v1 quad_perm:[0,1,2,3]
2571-
// GFX11: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0xff]
2570+
v_sin_f16 v5.l, v1.l quad_perm:[0,1,2,3]
2571+
// GFX11: v_sin_f16_dpp v5.l, v1.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0xff]
25722572

2573-
v_sin_f16 v5, v1 row_mirror
2574-
// GFX11: v_sin_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x40,0x01,0xff]
2573+
v_sin_f16 v5.l, v1.l row_mirror
2574+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x40,0x01,0xff]
25752575

2576-
v_sin_f16 v5, v1 row_half_mirror
2577-
// GFX11: v_sin_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x41,0x01,0xff]
2576+
v_sin_f16 v5.l, v1.l row_half_mirror
2577+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x41,0x01,0xff]
25782578

2579-
v_sin_f16 v5, v1 row_shl:1
2580-
// GFX11: v_sin_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x01,0x01,0xff]
2579+
v_sin_f16 v5.l, v1.l row_shl:1
2580+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x01,0x01,0xff]
25812581

2582-
v_sin_f16 v5, v1 row_shl:15
2583-
// GFX11: v_sin_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x0f,0x01,0xff]
2582+
v_sin_f16 v5.l, v1.l row_shl:15
2583+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x0f,0x01,0xff]
25842584

2585-
v_sin_f16 v5, v1 row_shr:1
2586-
// GFX11: v_sin_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x11,0x01,0xff]
2585+
v_sin_f16 v5.l, v1.l row_shr:1
2586+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x11,0x01,0xff]
25872587

2588-
v_sin_f16 v5, v1 row_shr:15
2589-
// GFX11: v_sin_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1f,0x01,0xff]
2588+
v_sin_f16 v5.l, v1.l row_shr:15
2589+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1f,0x01,0xff]
25902590

2591-
v_sin_f16 v5, v1 row_ror:1
2592-
// GFX11: v_sin_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x21,0x01,0xff]
2591+
v_sin_f16 v5.l, v1.l row_ror:1
2592+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x21,0x01,0xff]
25932593

2594-
v_sin_f16 v5, v1 row_ror:15
2595-
// GFX11: v_sin_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x2f,0x01,0xff]
2594+
v_sin_f16 v5.l, v1.l row_ror:15
2595+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x2f,0x01,0xff]
25962596

2597-
v_sin_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
2598-
// GFX11: v_sin_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x50,0x01,0xff]
2597+
v_sin_f16 v5.l, v1.l row_share:0 row_mask:0xf bank_mask:0xf
2598+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x50,0x01,0xff]
25992599

2600-
v_sin_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
2601-
// GFX11: v_sin_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x5f,0x01,0x01]
2600+
v_sin_f16 v5.l, v1.l row_share:15 row_mask:0x0 bank_mask:0x1
2601+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x5f,0x01,0x01]
26022602

2603-
v_sin_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
2604-
// GFX11: v_sin_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x60,0x09,0x13]
2603+
v_sin_f16 v5.l, v1.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
2604+
// GFX11: v_sin_f16_dpp v5.l, v1.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x60,0x09,0x13]
26052605

2606-
v_sin_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
2607-
// GFX11: v_sin_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xc0,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
2606+
v_sin_f16 v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
2607+
// GFX11: v_sin_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xc0,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
2608+
2609+
v_sin_f16 v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
2610+
// GFX11: v_sin_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc0,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
2611+
2612+
v_sin_f16 v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
2613+
// GFX11: v_sin_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0xc0,0x0a,0x7f,0x81,0x60,0x09,0x13]
2614+
2615+
v_sin_f16 v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
2616+
// GFX11: v_sin_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xc0,0xfe,0x7f,0xff,0x6f,0x35,0x30]
26082617

26092618
v_sin_f32 v5, v1 quad_perm:[3,2,1,0]
26102619
// GFX11: v_sin_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x1b,0x00,0xff]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s

Lines changed: 15 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -596,14 +596,23 @@ v_sat_pk_u8_i16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
596596
v_sat_pk_u8_i16 v127, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
597597
// GFX11: v_sat_pk_u8_i16_dpp v127, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xc4,0xfe,0x7e,0xff,0x00,0x00,0x00]
598598

599-
v_sin_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
600-
// GFX11: v_sin_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc0,0x0a,0x7e,0x01,0x77,0x39,0x05]
599+
v_sin_f16 v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0]
600+
// GFX11: v_sin_f16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc0,0x0a,0x7e,0x01,0x77,0x39,0x05]
601601

602-
v_sin_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
603-
// GFX11: v_sin_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xc0,0x0a,0x7e,0x01,0x77,0x39,0x05]
602+
v_sin_f16 v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1
603+
// GFX11: v_sin_f16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xc0,0x0a,0x7e,0x01,0x77,0x39,0x05]
604604

605-
v_sin_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
606-
// GFX11: v_sin_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xc0,0xfe,0x7e,0x7f,0x00,0x00,0x00]
605+
v_sin_f16 v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
606+
// GFX11: v_sin_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xc0,0xfe,0x7e,0x7f,0x00,0x00,0x00]
607+
608+
v_sin_f16 v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0]
609+
// GFX11: v_sin_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc0,0xfe,0x7e,0x7f,0x77,0x39,0x05]
610+
611+
v_sin_f16 v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] fi:1
612+
// GFX11: v_sin_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xc0,0x0a,0x7f,0x81,0x77,0x39,0x05]
613+
614+
v_sin_f16 v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
615+
// GFX11: v_sin_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xc0,0xfe,0x7f,0xff,0x00,0x00,0x00]
607616

608617
v_sin_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
609618
// GFX11: v_sin_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x6a,0x0a,0x7e,0x01,0x77,0x39,0x05]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -719,6 +719,12 @@ v_sat_pk_u8_i16_e32 v199, v5 quad_perm:[3,2,1,0]
719719
v_sin_f16_e32 v128, 0xfe0b
720720
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
721721

722+
v_sin_f16_e32 v128.h, 0xfe0b
723+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
724+
725+
v_sin_f16_e32 v128.l, 0xfe0b
726+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
727+
722728
v_sin_f16_e32 v255, v1
723729
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
724730

@@ -728,6 +734,24 @@ v_sin_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
728734
v_sin_f16_e32 v255, v1 quad_perm:[3,2,1,0]
729735
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
730736

737+
v_sin_f16_e32 v255.h, v1.h
738+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
739+
740+
v_sin_f16_e32 v255.h, v1.h dpp8:[7,6,5,4,3,2,1,0]
741+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
742+
743+
v_sin_f16_e32 v255.h, v1.h quad_perm:[3,2,1,0]
744+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
745+
746+
v_sin_f16_e32 v255.l, v1.l
747+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
748+
749+
v_sin_f16_e32 v255.l, v1.l dpp8:[7,6,5,4,3,2,1,0]
750+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
751+
752+
v_sin_f16_e32 v255.l, v1.l quad_perm:[3,2,1,0]
753+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
754+
731755
v_sin_f16_e32 v5, v199
732756
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
733757

@@ -737,6 +761,24 @@ v_sin_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
737761
v_sin_f16_e32 v5, v199 quad_perm:[3,2,1,0]
738762
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
739763

764+
v_sin_f16_e32 v5.h, v199.h
765+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
766+
767+
v_sin_f16_e32 v5.h, v199.h dpp8:[7,6,5,4,3,2,1,0]
768+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
769+
770+
v_sin_f16_e32 v5.h, v199.h quad_perm:[3,2,1,0]
771+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
772+
773+
v_sin_f16_e32 v5.l, v199.l
774+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
775+
776+
v_sin_f16_e32 v5.l, v199.l dpp8:[7,6,5,4,3,2,1,0]
777+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
778+
779+
v_sin_f16_e32 v5.l, v199.l quad_perm:[3,2,1,0]
780+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
781+
740782
v_sqrt_f16_e32 v128.h, 0xfe0b
741783
// GFX11: :[[@LINE-1]]:16: error: invalid operand for instruction
742784

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