We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 980c203 commit c88a7c2Copy full SHA for c88a7c2
llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -1517,11 +1517,10 @@ class MIMG_IntersectRay_Helper<bit Is64, bit IsA16, bit isDual, bit isBVH8> {
1517
int GFX11PlusNSAAddrs = !if(IsA16, 4, 5);
1518
RegisterClass node_ptr_type = !if(Is64, VReg_64, VGPR_32);
1519
list<RegisterClass> GFX11PlusAddrTypes =
1520
- !if(isBVH8, [VReg_64, VReg_64, VReg_96, VReg_96, VGPR_32],
1521
- !if(isDual, [VReg_64, VReg_64, VReg_96, VReg_96, VReg_64],
1522
- !if(IsA16,
1523
- [node_ptr_type, VGPR_32, VReg_96, VReg_96],
1524
- [node_ptr_type, VGPR_32, VReg_96, VReg_96, VReg_96])));
+ !cond(!eq(isBVH8, 1) : [node_ptr_type, VReg_64, VReg_96, VReg_96, VGPR_32],
+ !eq(isDual, 1) : [node_ptr_type, VReg_64, VReg_96, VReg_96, VReg_64],
+ !eq(IsA16, 0) : [node_ptr_type, VGPR_32, VReg_96, VReg_96, VReg_96],
+ !eq(IsA16, 1) : [node_ptr_type, VGPR_32, VReg_96, VReg_96]);
1525
}
1526
1527
class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterClass AddrRC>
0 commit comments