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[DAG] visitOR/visitORLike - merge repeated SDLoc calls.
1 parent bfd1944 commit c88b84d

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-17
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1 file changed

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llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 15 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -457,7 +457,7 @@ namespace {
457457
SDValue visitAND(SDNode *N);
458458
SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
459459
SDValue visitOR(SDNode *N);
460-
SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N);
460+
SDValue visitORLike(SDValue N0, SDValue N1, const SDLoc &DL);
461461
SDValue visitXOR(SDNode *N);
462462
SDValue SimplifyVCastOp(SDNode *N, const SDLoc &DL);
463463
SDValue SimplifyVBinOp(SDNode *N, const SDLoc &DL);
@@ -7566,9 +7566,8 @@ SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
75667566

75677567
/// This contains all DAGCombine rules which reduce two values combined by
75687568
/// an Or operation to a single value \see visitANDLike().
7569-
SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, SDNode *N) {
7569+
SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, const SDLoc &DL) {
75707570
EVT VT = N1.getValueType();
7571-
SDLoc DL(N);
75727571

75737572
// fold (or x, undef) -> -1
75747573
if (!LegalOperations && (N0.isUndef() || N1.isUndef()))
@@ -7702,23 +7701,24 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
77027701
SDValue N0 = N->getOperand(0);
77037702
SDValue N1 = N->getOperand(1);
77047703
EVT VT = N1.getValueType();
7704+
SDLoc DL(N);
77057705

77067706
// x | x --> x
77077707
if (N0 == N1)
77087708
return N0;
77097709

77107710
// fold (or c1, c2) -> c1|c2
7711-
if (SDValue C = DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N), VT, {N0, N1}))
7711+
if (SDValue C = DAG.FoldConstantArithmetic(ISD::OR, DL, VT, {N0, N1}))
77127712
return C;
77137713

77147714
// canonicalize constant to RHS
77157715
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
77167716
!DAG.isConstantIntBuildVectorOrConstantInt(N1))
7717-
return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
7717+
return DAG.getNode(ISD::OR, DL, VT, N1, N0);
77187718

77197719
// fold vector ops
77207720
if (VT.isVector()) {
7721-
if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N)))
7721+
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL))
77227722
return FoldedVOp;
77237723

77247724
// fold (or x, 0) -> x, vector edition
@@ -7728,7 +7728,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
77287728
// fold (or x, -1) -> -1, vector edition
77297729
if (ISD::isConstantSplatVectorAllOnes(N1.getNode()))
77307730
// do not return N1, because undef node may exist in N1
7731-
return DAG.getAllOnesConstant(SDLoc(N), N1.getValueType());
7731+
return DAG.getAllOnesConstant(DL, N1.getValueType());
77327732

77337733
// fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask)
77347734
// Do this only if the resulting type / shuffle is legal.
@@ -7778,10 +7778,8 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
77787778
if (CanFold) {
77797779
SDValue NewLHS = ZeroN00 ? N0.getOperand(1) : N0.getOperand(0);
77807780
SDValue NewRHS = ZeroN10 ? N1.getOperand(1) : N1.getOperand(0);
7781-
77827781
SDValue LegalShuffle =
7783-
TLI.buildLegalVectorShuffle(VT, SDLoc(N), NewLHS, NewRHS,
7784-
Mask, DAG);
7782+
TLI.buildLegalVectorShuffle(VT, DL, NewLHS, NewRHS, Mask, DAG);
77857783
if (LegalShuffle)
77867784
return LegalShuffle;
77877785
}
@@ -7808,7 +7806,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
78087806
if (SDValue R = foldAndOrOfSETCC(N, DAG))
78097807
return R;
78107808

7811-
if (SDValue Combined = visitORLike(N0, N1, N))
7809+
if (SDValue Combined = visitORLike(N0, N1, DL))
78127810
return Combined;
78137811

78147812
if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N))
@@ -7821,12 +7819,12 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
78217819
return BSwap;
78227820

78237821
// reassociate or
7824-
if (SDValue ROR = reassociateOps(ISD::OR, SDLoc(N), N0, N1, N->getFlags()))
7822+
if (SDValue ROR = reassociateOps(ISD::OR, DL, N0, N1, N->getFlags()))
78257823
return ROR;
78267824

78277825
// Fold or(vecreduce(x), vecreduce(y)) -> vecreduce(or(x, y))
7828-
if (SDValue SD = reassociateReduction(ISD::VECREDUCE_OR, ISD::OR, SDLoc(N),
7829-
VT, N0, N1))
7826+
if (SDValue SD =
7827+
reassociateReduction(ISD::VECREDUCE_OR, ISD::OR, DL, VT, N0, N1))
78307828
return SD;
78317829

78327830
// Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
@@ -7840,7 +7838,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
78407838
{N1, N0.getOperand(1)})) {
78417839
SDValue IOR = DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1);
78427840
AddToWorklist(IOR.getNode());
7843-
return DAG.getNode(ISD::AND, SDLoc(N), VT, COR, IOR);
7841+
return DAG.getNode(ISD::AND, DL, VT, COR, IOR);
78447842
}
78457843
}
78467844

@@ -7855,7 +7853,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
78557853
return V;
78567854

78577855
// See if this is some rotate idiom.
7858-
if (SDValue Rot = MatchRotate(N0, N1, SDLoc(N)))
7856+
if (SDValue Rot = MatchRotate(N0, N1, DL))
78597857
return Rot;
78607858

78617859
if (SDValue Load = MatchLoadCombine(N))
@@ -11534,7 +11532,7 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
1153411532
N2_2, Flags);
1153511533
}
1153611534
// Otherwise see if we can optimize to a better pattern.
11537-
if (SDValue Combined = visitORLike(N0, N2_0, N))
11535+
if (SDValue Combined = visitORLike(N0, N2_0, DL))
1153811536
return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Combined, N1,
1153911537
N2_2, Flags);
1154011538
}

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