[RISCV][VCIX] Add vcix_state to GNU inline assembly register set

Resolved #106700.
This enables inline asm to have vcix_state to be a clobbered register
thus disable reordering between VCIX intrinsics and inline asm.

Author: 4vtomat

clang/lib/Basic/Targets/RISCV.cpp

@@ -44,7 +44,7 @@ ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const {
       "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
 
       // CSRs
-      "fflags", "frm", "vtype", "vl", "vxsat", "vxrm"
+      "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"
     };
   // clang-format on
   return llvm::ArrayRef(GCCRegNames);

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

@@ -666,3 +666,7 @@ def SSP    : RISCVReg<0, "ssp">;
 
 // Dummy SiFive VCIX state register
 def SF_VCIX_STATE : RISCVReg<0, "sf_vcix_state">;
+def : RISCVRegisterClass<[XLenVT], 32, (add SF_VCIX_STATE)> {
+  let RegInfos = XLenRI;
+  let isAllocatable = 0;
+}

llvm/test/CodeGen/RISCV/inline-asm-xsfvcp.ll

@@ -8,15 +8,15 @@
 define void @test_reorder(<vscale x 1 x i64> %vreg) {
 ; CHECK-LABEL: test_reorder:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
+; CHECK-NEXT:    sf.vc.iv 0, 0, v8, 0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    sf.vc.vv 3, 0, v8, v8
 ; CHECK-EMPTY:
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
-; CHECK-NEXT:    sf.vc.iv 0, 0, v8, 0
 ; CHECK-NEXT:    ret
 entry:
   call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 0, iXLen 0, <vscale x 1 x i64> %vreg, iXLen 0, iXLen 0)
-  call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;", "=r,^vr,~{memory},~{vl},~{vcix_state}"(<vscale x 1 x i64> %vreg)
+  call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;", "=r,^vr,~{memory},~{vl},~{sf_vcix_state}"(<vscale x 1 x i64> %vreg)
   ret void
 }