fixup! [RISCV] RISCV vector calling convention (2/2)

Author: 4vtomat

llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp

@@ -34,7 +34,7 @@ struct RISCVOutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
   // Whether this is assigning args for a return.
   bool IsRet;
 
-  RVVArgDispatcher RVVDispatcher;
+  RVVArgDispatcher &RVVDispatcher;
 
 public:
   RISCVOutgoingValueAssigner(
@@ -408,7 +408,8 @@ bool RISCVCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
   SmallVector<ArgInfo, 4> SplitRetInfos;
   splitToValueTypes(OrigRetInfo, SplitRetInfos, DL, CC);
 
-  RVVArgDispatcher Dispatcher{&MF, getTLI<RISCVTargetLowering>(), true};
+  RVVArgDispatcher Dispatcher{&MF, getTLI<RISCVTargetLowering>(),
+                              F.getReturnType()};
   RISCVOutgoingValueAssigner Assigner(
       CC == CallingConv::Fast ? RISCV::CC_RISCV_FastCC : RISCV::CC_RISCV,
       /*IsRet=*/true, Dispatcher);
@@ -520,6 +521,7 @@ bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
   CallingConv::ID CC = F.getCallingConv();
 
   SmallVector<ArgInfo, 32> SplitArgInfos;
+  std::vector<Type *> TypeList;
   unsigned Index = 0;
   for (auto &Arg : F.args()) {
     // Construct the ArgInfo object from destination register and argument type.
@@ -531,10 +533,12 @@ bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
     // correspondingly and appended to SplitArgInfos.
     splitToValueTypes(AInfo, SplitArgInfos, DL, CC);
 
+    TypeList.push_back(Arg.getType());
+
     ++Index;
   }
 
-  RVVArgDispatcher Dispatcher{&MF, getTLI<RISCVTargetLowering>(), false};
+  RVVArgDispatcher Dispatcher{&MF, getTLI<RISCVTargetLowering>(), TypeList};
   RISCVIncomingValueAssigner Assigner(
       CC == CallingConv::Fast ? RISCV::CC_RISCV_FastCC : RISCV::CC_RISCV,
       /*IsRet=*/false, Dispatcher);
@@ -575,11 +579,13 @@ bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
 
   SmallVector<ArgInfo, 32> SplitArgInfos;
   SmallVector<ISD::OutputArg, 8> Outs;
+  std::vector<Type *> TypeList;
   for (auto &AInfo : Info.OrigArgs) {
     // Handle any required unmerging of split value types from a given VReg into
     // physical registers. ArgInfo objects are constructed correspondingly and
     // appended to SplitArgInfos.
     splitToValueTypes(AInfo, SplitArgInfos, DL, CC);
+    TypeList.push_back(AInfo.Ty);
   }
 
   // TODO: Support tail calls.
@@ -597,8 +603,7 @@ bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
   Call.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
 
-  RVVArgDispatcher ArgDispatcher{&MF, getTLI<RISCVTargetLowering>(), false,
-                                 nullptr, &Info};
+  RVVArgDispatcher ArgDispatcher{&MF, getTLI<RISCVTargetLowering>(), TypeList};
   RISCVOutgoingValueAssigner ArgAssigner(
       CC == CallingConv::Fast ? RISCV::CC_RISCV_FastCC : RISCV::CC_RISCV,
       /*IsRet=*/false, ArgDispatcher);
@@ -629,7 +634,8 @@ bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
   SmallVector<ArgInfo, 4> SplitRetInfos;
   splitToValueTypes(Info.OrigRet, SplitRetInfos, DL, CC);
 
-  RVVArgDispatcher RetDispatcher{&MF, getTLI<RISCVTargetLowering>(), true};
+  RVVArgDispatcher RetDispatcher{&MF, getTLI<RISCVTargetLowering>(),
+                                 F.getReturnType()};
   RISCVIncomingValueAssigner RetAssigner(
       CC == CallingConv::Fast ? RISCV::CC_RISCV_FastCC : RISCV::CC_RISCV,
       /*IsRet=*/true, RetDispatcher);

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -18129,7 +18129,13 @@ void RISCVTargetLowering::analyzeInputArgs(
   unsigned NumArgs = Ins.size();
   FunctionType *FType = MF.getFunction().getFunctionType();
 
-  RVVArgDispatcher Dispatcher{&MF, this, IsRet};
+  std::vector<Type *> TypeList;
+  if (IsRet)
+    TypeList.push_back(MF.getFunction().getReturnType());
+  else
+    for (const Argument &Arg : MF.getFunction().args())
+      TypeList.push_back(Arg.getType());
+  RVVArgDispatcher Dispatcher{&MF, this, TypeList};
 
   for (unsigned i = 0; i != NumArgs; ++i) {
     MVT ArgVT = Ins[i].VT;
@@ -18158,7 +18164,13 @@ void RISCVTargetLowering::analyzeOutputArgs(
     CallLoweringInfo *CLI, RISCVCCAssignFn Fn) const {
   unsigned NumArgs = Outs.size();
 
-  RVVArgDispatcher Dispatcher{&MF, this, IsRet, CLI};
+  std::vector<Type *> TypeList;
+  if (IsRet)
+    TypeList.push_back(MF.getFunction().getReturnType());
+  else if (CLI)
+    for (const TargetLowering::ArgListEntry &Arg : CLI->getArgs())
+      TypeList.push_back(Arg.Ty);
+  RVVArgDispatcher Dispatcher{&MF, this, TypeList};
 
   for (unsigned i = 0; i != NumArgs; i++) {
     MVT ArgVT = Outs[i].VT;
@@ -19061,7 +19073,8 @@ bool RISCVTargetLowering::CanLowerReturn(
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
 
-  RVVArgDispatcher Dispatcher{&MF, this, true};
+  std::vector<Type *> TypeList = {MF.getFunction().getReturnType()};
+  RVVArgDispatcher Dispatcher{&MF, this, TypeList};
 
   for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
     MVT VT = Outs[i].VT;
@@ -20904,20 +20917,9 @@ void RVVArgDispatcher::constructHelper(Type *Ty) {
   }
 }
 
-void RVVArgDispatcher::construct(bool IsRet) {
-  const Function &F = MF->getFunction();
-
-  if (IsRet)
-    constructHelper(F.getReturnType());
-  else if (CLI)
-    for (const TargetLowering::ArgListEntry &Arg : CLI->getArgs())
-      constructHelper(Arg.Ty);
-  else if (GISelCLI)
-    for (const CallLowering::ArgInfo &Arg : GISelCLI->OrigArgs)
-      constructHelper(Arg.Ty);
-  else
-    for (const Argument &Arg : F.args())
-      constructHelper(Arg.getType());
+void RVVArgDispatcher::construct(std::vector<Type *> &TypeList) {
+  for (Type *Ty : TypeList)
+    constructHelper(Ty);
 
   for (auto &Info : RVVArgInfos)
     if (Info.NF == 1 && Info.VT.getVectorElementType() == MVT::i1) {

llvm/lib/Target/RISCV/RISCVISelLowering.h

@@ -1022,14 +1022,18 @@ class RVVArgDispatcher {
     bool FirstVMask = false;
   };
 
-  RVVArgDispatcher() = default;
   RVVArgDispatcher(const MachineFunction *MF, const RISCVTargetLowering *TLI,
-                   bool IsRet, TargetLowering::CallLoweringInfo *CLI = nullptr,
-                   CallLowering::CallLoweringInfo *GISelCLI = nullptr)
-      : MF(MF), TLI(TLI), CLI(CLI), GISelCLI(GISelCLI) {
-    assert((!CLI || !GISelCLI) &&
-           "ISel and Global ISel can't co-exist at the same time");
-    construct(IsRet);
+                   std::vector<Type *> &TypeList)
+      : MF(MF), TLI(TLI) {
+    construct(TypeList);
+    compute();
+  }
+
+  RVVArgDispatcher(const MachineFunction *MF, const RISCVTargetLowering *TLI,
+                   Type *Ty)
+      : MF(MF), TLI(TLI) {
+    std::vector<Type *> TypeList = {Ty};
+    construct(TypeList);
     compute();
   }
 
@@ -1046,7 +1050,7 @@ class RVVArgDispatcher {
 
   unsigned CurIdx = 0;
 
-  void construct(bool IsRet);
+  void construct(std::vector<Type *> &TypeList);
   void constructHelper(Type *Ty);
   void compute();
   void allocatePhysReg(unsigned NF = 1, unsigned LMul = 1,