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skip _ec ld insn when data size is lesser or equal to 32.
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llvm/lib/Target/AMDGPU/SMInstructions.td

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -171,15 +171,15 @@ multiclass SM_Pseudo_Loads<RegisterClass baseClass,
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// The constrained multi-dword load equivalents with early clobber flag at
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// the dst operand. They are needed only for codegen and there is no need for
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// their real opcodes.
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let SubtargetPredicate = isGFX8Plus,
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Constraints = !if(!gt(dstClass.RegTypes[0].Size, 32),
176-
"@earlyclobber $sdst", "") in {
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let PseudoInstr = NAME # !cast<OffsetMode>(IMM_Offset).Variant in
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def _IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, IMM_Offset>;
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let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_Offset).Variant in
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def _SGPR_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_Offset>;
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let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_IMM_Offset).Variant in
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def _SGPR_IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_IMM_Offset>;
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if !gt(dstClass.RegTypes[0].Size, 32) then {
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let SubtargetPredicate = isGFX8Plus, Constraints = "@earlyclobber $sdst" in {
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let PseudoInstr = NAME # !cast<OffsetMode>(IMM_Offset).Variant in
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def _IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, IMM_Offset>;
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let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_Offset).Variant in
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def _SGPR_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_Offset>;
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let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_IMM_Offset).Variant in
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def _SGPR_IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_IMM_Offset>;
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}
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}
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}
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