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[RISCV] Refactor GPRF64 register class to make it usable for Zacas. (#77408)
-Rename to GPRPair. -Rename registers to be named like X10_X11 instead of X10_PD. Except X0 which is now X0_Pair since it is not paired with X1. -Use unknown size and offset for the subreg indices. This might be a functional change, but does not affect any lit tests.
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7 files changed

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-45
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7 files changed

+59
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‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1295,7 +1295,7 @@ unsigned RISCVAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
12951295
const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
12961296

12971297
for (unsigned I = 0; I < MCID.NumOperands; ++I) {
1298-
if (MCID.operands()[I].RegClass == RISCV::GPRPF64RegClassID) {
1298+
if (MCID.operands()[I].RegClass == RISCV::GPRPairRegClassID) {
12991299
const auto &Op = Inst.getOperand(I);
13001300
assert(Op.isReg());
13011301

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -171,7 +171,7 @@ static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo,
171171
return MCDisassembler::Success;
172172
}
173173

174-
static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint32_t RegNo,
174+
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo,
175175
uint64_t Address,
176176
const MCDisassembler *Decoder) {
177177
if (RegNo >= 32 || RegNo & 1)

‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -308,8 +308,10 @@ bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
308308
MachineBasicBlock::iterator MBBI) {
309309
DebugLoc DL = MBBI->getDebugLoc();
310310
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
311-
Register Lo = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32);
312-
Register Hi = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32_hi);
311+
Register Lo =
312+
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
313+
Register Hi =
314+
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
313315
BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
314316
.addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
315317
.addReg(MBBI->getOperand(1).getReg())
@@ -342,8 +344,10 @@ bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
342344
MachineBasicBlock::iterator MBBI) {
343345
DebugLoc DL = MBBI->getDebugLoc();
344346
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
345-
Register Lo = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32);
346-
Register Hi = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32_hi);
347+
Register Lo =
348+
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
349+
Register Hi =
350+
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
347351

348352
// If the register of operand 1 is equal to the Lo register, then swap the
349353
// order of loading the Lo and Hi statements.

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
138138
if (Subtarget.is64Bit())
139139
addRegisterClass(MVT::f64, &RISCV::GPRRegClass);
140140
else
141-
addRegisterClass(MVT::f64, &RISCV::GPRPF64RegClass);
141+
addRegisterClass(MVT::f64, &RISCV::GPRPairRegClass);
142142
}
143143

144144
static const MVT::SimpleValueType BoolVecVTs[] = {
@@ -16344,7 +16344,7 @@ static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
1634416344
Register SrcReg = MI.getOperand(2).getReg();
1634516345

1634616346
const TargetRegisterClass *SrcRC = MI.getOpcode() == RISCV::SplitF64Pseudo_INX
16347-
? &RISCV::GPRPF64RegClass
16347+
? &RISCV::GPRPairRegClass
1634816348
: &RISCV::FPR64RegClass;
1634916349
int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(MF);
1635016350

@@ -16383,7 +16383,7 @@ static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI,
1638316383
Register HiReg = MI.getOperand(2).getReg();
1638416384

1638516385
const TargetRegisterClass *DstRC =
16386-
MI.getOpcode() == RISCV::BuildPairF64Pseudo_INX ? &RISCV::GPRPF64RegClass
16386+
MI.getOpcode() == RISCV::BuildPairF64Pseudo_INX ? &RISCV::GPRPairRegClass
1638716387
: &RISCV::FPR64RegClass;
1638816388
int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(MF);
1638916389

@@ -18751,7 +18751,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1875118751
if (VT == MVT::f32 && Subtarget.hasStdExtZfinx())
1875218752
return std::make_pair(0U, &RISCV::GPRF32RegClass);
1875318753
if (VT == MVT::f64 && Subtarget.hasStdExtZdinx() && !Subtarget.is64Bit())
18754-
return std::make_pair(0U, &RISCV::GPRPF64RegClass);
18754+
return std::make_pair(0U, &RISCV::GPRPairRegClass);
1875518755
return std::make_pair(0U, &RISCV::GPRNoX0RegClass);
1875618756
case 'f':
1875718757
if (Subtarget.hasStdExtZfhmin() && VT == MVT::f16)
@@ -18933,7 +18933,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1893318933
// Subtarget into account.
1893418934
if (Res.second == &RISCV::GPRF16RegClass ||
1893518935
Res.second == &RISCV::GPRF32RegClass ||
18936-
Res.second == &RISCV::GPRPF64RegClass)
18936+
Res.second == &RISCV::GPRPairRegClass)
1893718937
return std::make_pair(Res.first, &RISCV::GPRRegClass);
1893818938

1893918939
return Res;

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -414,15 +414,16 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
414414
return;
415415
}
416416

417-
if (RISCV::GPRPF64RegClass.contains(DstReg, SrcReg)) {
418-
// Emit an ADDI for both parts of GPRPF64.
417+
if (RISCV::GPRPairRegClass.contains(DstReg, SrcReg)) {
418+
// Emit an ADDI for both parts of GPRPair.
419419
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI),
420-
TRI->getSubReg(DstReg, RISCV::sub_32))
421-
.addReg(TRI->getSubReg(SrcReg, RISCV::sub_32), getKillRegState(KillSrc))
420+
TRI->getSubReg(DstReg, RISCV::sub_gpr_even))
421+
.addReg(TRI->getSubReg(SrcReg, RISCV::sub_gpr_even),
422+
getKillRegState(KillSrc))
422423
.addImm(0);
423424
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI),
424-
TRI->getSubReg(DstReg, RISCV::sub_32_hi))
425-
.addReg(TRI->getSubReg(SrcReg, RISCV::sub_32_hi),
425+
TRI->getSubReg(DstReg, RISCV::sub_gpr_odd))
426+
.addReg(TRI->getSubReg(SrcReg, RISCV::sub_gpr_odd),
426427
getKillRegState(KillSrc))
427428
.addImm(0);
428429
return;
@@ -607,7 +608,7 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
607608
Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
608609
RISCV::SW : RISCV::SD;
609610
IsScalableVector = false;
610-
} else if (RISCV::GPRPF64RegClass.hasSubClassEq(RC)) {
611+
} else if (RISCV::GPRPairRegClass.hasSubClassEq(RC)) {
611612
Opcode = RISCV::PseudoRV32ZdinxSD;
612613
IsScalableVector = false;
613614
} else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
@@ -690,7 +691,7 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
690691
Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
691692
RISCV::LW : RISCV::LD;
692693
IsScalableVector = false;
693-
} else if (RISCV::GPRPF64RegClass.hasSubClassEq(RC)) {
694+
} else if (RISCV::GPRPairRegClass.hasSubClassEq(RC)) {
694695
Opcode = RISCV::PseudoRV32ZdinxLD;
695696
IsScalableVector = false;
696697
} else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {

‎llvm/lib/Target/RISCV/RISCVInstrInfoD.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -33,8 +33,8 @@ def AddrRegImmINX : ComplexPattern<iPTR, 2, "SelectAddrRegImmINX">;
3333

3434
// Zdinx
3535

36-
def GPRPF64AsFPR : AsmOperandClass {
37-
let Name = "GPRPF64AsFPR";
36+
def GPRPairAsFPR : AsmOperandClass {
37+
let Name = "GPRPairAsFPR";
3838
let ParserMethod = "parseGPRAsFPR";
3939
let PredicateMethod = "isGPRAsFPR";
4040
let RenderMethod = "addRegOperands";
@@ -52,8 +52,8 @@ def FPR64INX : RegisterOperand<GPR> {
5252
let DecoderMethod = "DecodeGPRRegisterClass";
5353
}
5454

55-
def FPR64IN32X : RegisterOperand<GPRPF64> {
56-
let ParserMatchClass = GPRPF64AsFPR;
55+
def FPR64IN32X : RegisterOperand<GPRPair> {
56+
let ParserMatchClass = GPRPairAsFPR;
5757
}
5858

5959
def DExt : ExtInfo<"", "", [HasStdExtD], f64, FPR64, FPR32, FPR64, ?>;
@@ -515,15 +515,15 @@ def PseudoFROUND_D_IN32X : PseudoFROUND<FPR64IN32X, f64>;
515515

516516
/// Loads
517517
let isCall = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 1 in
518-
def PseudoRV32ZdinxLD : Pseudo<(outs GPRPF64:$dst), (ins GPR:$rs1, simm12:$imm12), []>;
518+
def PseudoRV32ZdinxLD : Pseudo<(outs GPRPair:$dst), (ins GPR:$rs1, simm12:$imm12), []>;
519519
def : Pat<(f64 (load (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12))),
520520
(PseudoRV32ZdinxLD GPR:$rs1, simm12:$imm12)>;
521521

522522
/// Stores
523523
let isCall = 0, mayLoad = 0, mayStore = 1, Size = 8, isCodeGenOnly = 1 in
524-
def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPF64:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>;
525-
def : Pat<(store (f64 GPRPF64:$rs2), (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12)),
526-
(PseudoRV32ZdinxSD GPRPF64:$rs2, GPR:$rs1, simm12:$imm12)>;
524+
def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>;
525+
def : Pat<(store (f64 GPRPair:$rs2), (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12)),
526+
(PseudoRV32ZdinxSD GPRPair:$rs2, GPR:$rs1, simm12:$imm12)>;
527527

528528
/// Pseudo-instructions needed for the soft-float ABI with RV32D
529529

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Lines changed: 27 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,10 @@ def sub_vrm1_5 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_1>;
6363
def sub_vrm1_6 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_0>;
6464
def sub_vrm1_7 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_1>;
6565

66-
def sub_32_hi : SubRegIndex<32, 32>;
66+
// GPR sizes change with HwMode.
67+
// FIXME: Support HwMode in SubRegIndex?
68+
def sub_gpr_even : SubRegIndex<-1>;
69+
def sub_gpr_odd : SubRegIndex<-1, -1>;
6770
} // Namespace = "RISCV"
6871

6972
// Integer registers
@@ -118,6 +121,8 @@ def XLenVT : ValueTypeByHwMode<[RV32, RV64],
118121
// Allow f64 in GPR for ZDINX on RV64.
119122
def XLenFVT : ValueTypeByHwMode<[RV64],
120123
[f64]>;
124+
def XLenPairFVT : ValueTypeByHwMode<[RV32],
125+
[f64]>;
121126
def XLenRI : RegInfoByHwMode<
122127
[RV32, RV64],
123128
[RegInfo<32,32,32>, RegInfo<64,64,64>]>;
@@ -546,33 +551,37 @@ def DUMMY_REG_PAIR_WITH_X0 : RISCVReg<0, "0">;
546551
def GPRAll : GPRRegisterClass<(add GPR, DUMMY_REG_PAIR_WITH_X0)>;
547552

548553
let RegAltNameIndices = [ABIRegAltName] in {
549-
def X0_PD : RISCVRegWithSubRegs<0, X0.AsmName,
550-
[X0, DUMMY_REG_PAIR_WITH_X0],
551-
X0.AltNames> {
552-
let SubRegIndices = [sub_32, sub_32_hi];
554+
def X0_Pair : RISCVRegWithSubRegs<0, X0.AsmName,
555+
[X0, DUMMY_REG_PAIR_WITH_X0],
556+
X0.AltNames> {
557+
let SubRegIndices = [sub_gpr_even, sub_gpr_odd];
553558
let CoveredBySubRegs = 1;
554559
}
555560
foreach I = 1-15 in {
556561
defvar Index = !shl(I, 1);
562+
defvar IndexP1 = !add(Index, 1);
557563
defvar Reg = !cast<Register>("X"#Index);
558-
defvar RegP1 = !cast<Register>("X"#!add(Index,1));
559-
def X#Index#_PD : RISCVRegWithSubRegs<Index, Reg.AsmName,
560-
[Reg, RegP1],
561-
Reg.AltNames> {
562-
let SubRegIndices = [sub_32, sub_32_hi];
564+
defvar RegP1 = !cast<Register>("X"#IndexP1);
565+
def "X" # Index #"_X" # IndexP1 : RISCVRegWithSubRegs<Index,
566+
Reg.AsmName,
567+
[Reg, RegP1],
568+
Reg.AltNames> {
569+
let SubRegIndices = [sub_gpr_even, sub_gpr_odd];
563570
let CoveredBySubRegs = 1;
564571
}
565572
}
566573
}
567574

568-
let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in
569-
def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
570-
X10_PD, X12_PD, X14_PD, X16_PD,
571-
X6_PD,
572-
X28_PD, X30_PD,
573-
X8_PD,
574-
X18_PD, X20_PD, X22_PD, X24_PD, X26_PD,
575-
X0_PD, X2_PD, X4_PD
575+
let RegInfos = RegInfoByHwMode<[RV32, RV64],
576+
[RegInfo<64, 64, 64>, RegInfo<128, 128, 128>]>,
577+
DecoderMethod = "DecodeGPRPairRegisterClass" in
578+
def GPRPair : RegisterClass<"RISCV", [XLenPairFVT], 64, (add
579+
X10_X11, X12_X13, X14_X15, X16_X17,
580+
X6_X7,
581+
X28_X29, X30_X31,
582+
X8_X9,
583+
X18_X19, X20_X21, X22_X23, X24_X25, X26_X27,
584+
X0_Pair, X2_X3, X4_X5
576585
)>;
577586

578587
// The register class is added for inline assembly for vector mask types.

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