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fix result groups
1 parent bbca902 commit ca084f9

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2 files changed

+11
-9
lines changed

2 files changed

+11
-9
lines changed

mlir/lib/IR/AsmPrinter.cpp

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,8 @@ OpAsmParser::~OpAsmParser() = default;
7373
MLIRContext *AsmParser::getContext() const { return getBuilder().getContext(); }
7474

7575
/// Parse a type list.
76-
/// This is out-of-line to work-around https://github.com/llvm/llvm-project/issues/62918
76+
/// This is out-of-line to work-around
77+
/// https://github.com/llvm/llvm-project/issues/62918
7778
ParseResult AsmParser::parseTypeList(SmallVectorImpl<Type> &result) {
7879
return parseCommaSeparatedList(
7980
[&]() { return parseType(result.emplace_back()); });
@@ -1626,16 +1627,17 @@ void SSANameState::numberValuesInOp(Operation &op) {
16261627
}
16271628
}
16281629

1630+
unsigned numResults = op.getNumResults();
16291631
if (printerFlags.shouldUseNameLocAsPrefix() && !alreadySetNames) {
1630-
for (Value opResult : op.getResults()) {
1631-
if (isa<NameLoc>(opResult.getLoc())) {
1632-
auto nameLoc = cast<NameLoc>(opResult.getLoc());
1633-
setResultNameFn(opResult, nameLoc.getName());
1632+
if (numResults > 0) {
1633+
Value resultBegin = op.getResult(0);
1634+
if (isa<NameLoc>(resultBegin.getLoc())) {
1635+
auto nameLoc = cast<NameLoc>(resultBegin.getLoc());
1636+
setResultNameFn(resultBegin, nameLoc.getName());
16341637
}
16351638
}
16361639
}
16371640

1638-
unsigned numResults = op.getNumResults();
16391641
if (numResults == 0) {
16401642
// If value users should be printed, operations with no result need an id.
16411643
if (printerFlags.shouldPrintValueUsers()) {

mlir/test/IR/wrapping_op.mlir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,10 @@
55
// CHECK-GENERIC: "func.func"
66
// CHECK-GENERIC-SAME: sym_name = "wrapping_op"
77
func.func @wrapping_op(%arg0 : i32, %arg1 : f32) -> (i3, i2, i1) {
8-
// CHECK: %some_NameLoc, %some_NameLoc_0, %some_NameLoc_1 = test.wrapping_region wraps "some.op"(%arg1, %arg0) {test.attr = "attr"} : (f32, i32) -> (i1, i2, i3)
8+
// CHECK: %some_NameLoc:3 = test.wrapping_region wraps "some.op"(%arg1, %arg0) {test.attr = "attr"} : (f32, i32) -> (i1, i2, i3)
99
// CHECK-GENERIC: "test.wrapping_region"() ({
10-
// CHECK-GENERIC: %some_NameLoc_2, %some_NameLoc_3, %some_NameLoc_4 = "some.op"(%arg1, %arg0) {test.attr = "attr"} : (f32, i32) -> (i1, i2, i3) loc("some_NameLoc")
11-
// CHECK-GENERIC: "test.return"(%some_NameLoc_2, %some_NameLoc_3, %some_NameLoc_4) : (i1, i2, i3) -> () loc("some_NameLoc")
10+
// CHECK-GENERIC: %[[NESTED_RES:.*]]:3 = "some.op"(%arg1, %arg0) {test.attr = "attr"} : (f32, i32) -> (i1, i2, i3) loc("some_NameLoc")
11+
// CHECK-GENERIC: "test.return"(%[[NESTED_RES]]#0, %[[NESTED_RES]]#1, %[[NESTED_RES]]#2) : (i1, i2, i3) -> () loc("some_NameLoc")
1212
// CHECK-GENERIC: }) : () -> (i1, i2, i3) loc("some_NameLoc")
1313
%res:3 = test.wrapping_region wraps "some.op"(%arg1, %arg0) { test.attr = "attr" } : (f32, i32) -> (i1, i2, i3) loc("some_NameLoc")
1414
return %res#2, %res#1, %res#0 : i3, i2, i1

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