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farzonlfarzonl
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fix up copy paste errors in test cases
1 parent ec75e67 commit caebc70

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4 files changed

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‎llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll

Lines changed: 38 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -26,32 +26,32 @@
2626
; CHECK-HLSL-DAG: %[[#const_i32_0:]] = OpConstant %[[#int_32]] 0
2727
; CHECK-HLSL-DAG: %[[#const_i16_0:]] = OpConstant %[[#int_16]] 0
2828
; CHECK-HLSL-DAG: %[[#const_f64_0:]] = OpConstant %[[#float_64]] 0
29-
; CHECK-HLSL-DAG: %[[#const_f32_0:]] = OpConstant %[[#float_32:]] 0
30-
; CHECK-HLSL-DAG: %[[#const_f16_0:]] = OpConstant %[[#float_16:]] 0
31-
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i16:]] = OpConstantComposite %[[#vec4_16:]] %[[#const_i16_0:]] %[[#const_i16_0:]] %[[#const_i16_0:]] %[[#const_i16_0:]]
32-
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i32:]] = OpConstantComposite %[[#vec4_32:]] %[[#const_i32_0:]] %[[#const_i32_0:]] %[[#const_i32_0:]] %[[#const_i32_0:]]
33-
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i64:]] = OpConstantComposite %[[#vec4_64:]] %[[#const_i64_0:]] %[[#const_i64_0:]] %[[#const_i64_0:]] %[[#const_i64_0:]]
34-
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f16:]] = OpConstantComposite %[[#vec4_float_16:]] %[[#const_f16_0:]] %[[#const_f16_0:]] %[[#const_f16_0:]] %[[#const_f16_0:]]
35-
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f32:]] = OpConstantComposite %[[#vec4_float_32:]] %[[#const_f32_0:]] %[[#const_f32_0:]] %[[#const_f32_0:]] %[[#const_f32_0:]]
36-
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f64:]] = OpConstantComposite %[[#vec4_float_64:]] %[[#const_f64_0:]] %[[#const_f64_0:]] %[[#const_f64_0:]] %[[#const_f64_0:]]
29+
; CHECK-HLSL-DAG: %[[#const_f32_0:]] = OpConstant %[[#float_32]] 0
30+
; CHECK-HLSL-DAG: %[[#const_f16_0:]] = OpConstant %[[#float_16]] 0
31+
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i16:]] = OpConstantComposite %[[#vec4_16]] %[[#const_i16_0]] %[[#const_i16_0]] %[[#const_i16_0]] %[[#const_i16_0]]
32+
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i32:]] = OpConstantComposite %[[#vec4_32]] %[[#const_i32_0]] %[[#const_i32_0]] %[[#const_i32_0]] %[[#const_i32_0]]
33+
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i64:]] = OpConstantComposite %[[#vec4_64]] %[[#const_i64_0]] %[[#const_i64_0]] %[[#const_i64_0]] %[[#const_i64_0]]
34+
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f16:]] = OpConstantComposite %[[#vec4_float_16]] %[[#const_f16_0]] %[[#const_f16_0]] %[[#const_f16_0]] %[[#const_f16_0]]
35+
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f32:]] = OpConstantComposite %[[#vec4_float_32]] %[[#const_f32_0]] %[[#const_f32_0]] %[[#const_f32_0]] %[[#const_f32_0]]
36+
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f64:]] = OpConstantComposite %[[#vec4_float_64]] %[[#const_f64_0]] %[[#const_f64_0]] %[[#const_f64_0]] %[[#const_f64_0]]
3737

3838
; CHECK-OCL-DAG: %[[#const_i64_0:]] = OpConstantNull %[[#int_64]]
3939
; CHECK-OCL-DAG: %[[#const_i32_0:]] = OpConstantNull %[[#int_32]]
4040
; CHECK-OCL-DAG: %[[#const_i16_0:]] = OpConstantNull %[[#int_16]]
4141
; CHECK-OCL-DAG: %[[#const_f64_0:]] = OpConstantNull %[[#float_64]]
42-
; CHECK-OCL-DAG: %[[#const_f32_0:]] = OpConstantNull %[[#float_32:]]
43-
; CHECK-OCL-DAG: %[[#const_f16_0:]] = OpConstantNull %[[#float_16:]]
44-
; CHECK-OCL-DAG: %[[#vec4_const_zeros_i16:]] = OpConstantNull %[[#vec4_16:]]
45-
; CHECK-OCL-DAG: %[[#vec4_const_zeros_i32:]] = OpConstantNull %[[#vec4_32:]]
46-
; CHECK-OCL-DAG: %[[#vec4_const_zeros_i64:]] = OpConstantNull %[[#vec4_64:]]
47-
; CHECK-OCL-DAG: %[[#vec4_const_zeros_f16:]] = OpConstantNull %[[#vec4_float_16:]]
48-
; CHECK-OCL-DAG: %[[#vec4_const_zeros_f32:]] = OpConstantNull %[[#vec4_float_32:]]
49-
; CHECK-OCL-DAG: %[[#vec4_const_zeros_f64:]] = OpConstantNull %[[#vec4_float_64:]]
42+
; CHECK-OCL-DAG: %[[#const_f32_0:]] = OpConstantNull %[[#float_32]]
43+
; CHECK-OCL-DAG: %[[#const_f16_0:]] = OpConstantNull %[[#float_16]]
44+
; CHECK-OCL-DAG: %[[#vec4_const_zeros_i16:]] = OpConstantNull %[[#vec4_16]]
45+
; CHECK-OCL-DAG: %[[#vec4_const_zeros_i32:]] = OpConstantNull %[[#vec4_32]]
46+
; CHECK-OCL-DAG: %[[#vec4_const_zeros_i64:]] = OpConstantNull %[[#vec4_64]]
47+
; CHECK-OCL-DAG: %[[#vec4_const_zeros_f16:]] = OpConstantNull %[[#vec4_float_16]]
48+
; CHECK-OCL-DAG: %[[#vec4_const_zeros_f32:]] = OpConstantNull %[[#vec4_float_32]]
49+
; CHECK-OCL-DAG: %[[#vec4_const_zeros_f64:]] = OpConstantNull %[[#vec4_float_64]]
5050

5151
define noundef i1 @all_int64_t(i64 noundef %p0) {
5252
entry:
5353
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
54-
; CHECK: %[[#]] = OpINotEqual %[[#bool:]] %[[#arg0:]] %[[#const_i64_0:]]
54+
; CHECK: %[[#]] = OpINotEqual %[[#bool]] %[[#arg0]] %[[#const_i64_0]]
5555
%hlsl.all = call i1 @llvm.spv.all.i64(i64 %p0)
5656
ret i1 %hlsl.all
5757
}
@@ -60,7 +60,7 @@ entry:
6060
define noundef i1 @all_int(i32 noundef %p0) {
6161
entry:
6262
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
63-
; CHECK: %[[#]] = OpINotEqual %[[#bool:]] %[[#arg0:]] %[[#const_i32_0:]]
63+
; CHECK: %[[#]] = OpINotEqual %[[#bool]] %[[#arg0]] %[[#const_i32_0]]
6464
%hlsl.all = call i1 @llvm.spv.all.i32(i32 %p0)
6565
ret i1 %hlsl.all
6666
}
@@ -69,15 +69,15 @@ entry:
6969
define noundef i1 @all_int16_t(i16 noundef %p0) {
7070
entry:
7171
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
72-
; CHECK: %[[#]] = OpINotEqual %[[#bool:]] %[[#arg0:]] %[[#const_i16_0:]]
72+
; CHECK: %[[#]] = OpINotEqual %[[#bool]] %[[#arg0]] %[[#const_i16_0]]
7373
%hlsl.all = call i1 @llvm.spv.all.i16(i16 %p0)
7474
ret i1 %hlsl.all
7575
}
7676

7777
define noundef i1 @all_double(double noundef %p0) {
7878
entry:
7979
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
80-
; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool:]] %[[#arg0:]] %[[#const_f64_0:]]
80+
; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool]] %[[#arg0]] %[[#const_f64_0]]
8181
%hlsl.all = call i1 @llvm.spv.all.f64(double %p0)
8282
ret i1 %hlsl.all
8383
}
@@ -86,7 +86,7 @@ entry:
8686
define noundef i1 @all_float(float noundef %p0) {
8787
entry:
8888
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
89-
; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool:]] %[[#arg0:]] %[[#const_f32_0:]]
89+
; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool]] %[[#arg0]] %[[#const_f32_0]]
9090
%hlsl.all = call i1 @llvm.spv.all.f32(float %p0)
9191
ret i1 %hlsl.all
9292
}
@@ -95,78 +95,78 @@ entry:
9595
define noundef i1 @all_half(half noundef %p0) {
9696
entry:
9797
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
98-
; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool:]] %[[#arg0:]] %[[#const_f16_0:]]
98+
; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool]] %[[#arg0]] %[[#const_f16_0]]
9999
%hlsl.all = call i1 @llvm.spv.all.f16(half %p0)
100100
ret i1 %hlsl.all
101101
}
102102

103103

104104
define noundef i1 @all_bool4(<4 x i1> noundef %p0) {
105105
entry:
106-
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
107-
; CHECK: %[[#]] = OpAll %[[#vec4_bool:]] %[[#arg0:]]
106+
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec4_bool]]
107+
; CHECK: %[[#]] = OpAll %[[#bool]] %[[#arg0]]
108108
%hlsl.all = call i1 @llvm.spv.all.v4i1(<4 x i1> %p0)
109109
ret i1 %hlsl.all
110110
}
111111

112112
define noundef i1 @all_short4(<4 x i16> noundef %p0) {
113113
entry:
114114
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
115-
; CHECK: %[[#shortVecNotEq:]] = OpINotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_i16:]]
116-
; CHECK: %[[#]] = OpAll %[[#bool:]] %[[#shortVecNotEq:]]
115+
; CHECK: %[[#shortVecNotEq:]] = OpINotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_i16]]
116+
; CHECK: %[[#]] = OpAll %[[#bool]] %[[#shortVecNotEq]]
117117
%hlsl.all = call i1 @llvm.spv.all.v4i16(<4 x i16> %p0)
118118
ret i1 %hlsl.all
119119
}
120120

121121
define noundef i1 @all_int4(<4 x i32> noundef %p0) {
122122
entry:
123123
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
124-
; CHECK: %[[#i32VecNotEq:]] = OpINotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_i32:]]
125-
; CHECK: %[[#]] = OpAll %[[#bool:]] %[[#i32VecNotEq:]]
124+
; CHECK: %[[#i32VecNotEq:]] = OpINotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_i32]]
125+
; CHECK: %[[#]] = OpAll %[[#bool]] %[[#i32VecNotEq]]
126126
%hlsl.all = call i1 @llvm.spv.all.v4i32(<4 x i32> %p0)
127127
ret i1 %hlsl.all
128128
}
129129

130130
define noundef i1 @all_int64_t4(<4 x i64> noundef %p0) {
131131
entry:
132132
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
133-
; CHECK: %[[#i64VecNotEq:]] = OpINotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_i64:]]
134-
; CHECK: %[[#]] = OpAll %[[#bool:]] %[[#i64VecNotEq]]
133+
; CHECK: %[[#i64VecNotEq:]] = OpINotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_i64]]
134+
; CHECK: %[[#]] = OpAll %[[#bool]] %[[#i64VecNotEq]]
135135
%hlsl.all = call i1 @llvm.spv.all.v4i64(<4 x i64> %p0)
136136
ret i1 %hlsl.all
137137
}
138138

139139
define noundef i1 @all_half4(<4 x half> noundef %p0) {
140140
entry:
141141
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
142-
; CHECK: %[[#f16VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_f16:]]
143-
; CHECK: %[[#]] = OpAll %[[#bool]] %[[#f16VecNotEq:]]
142+
; CHECK: %[[#f16VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_f16]]
143+
; CHECK: %[[#]] = OpAll %[[#bool]] %[[#f16VecNotEq]]
144144
%hlsl.all = call i1 @llvm.spv.all.v4f16(<4 x half> %p0)
145145
ret i1 %hlsl.all
146146
}
147147

148148
define noundef i1 @all_float4(<4 x float> noundef %p0) {
149149
entry:
150150
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
151-
; CHECK: %[[#f32VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_f32:]]
152-
; CHECK: %[[#]] = OpAll %[[#bool:]] %[[#f32VecNotEq:]]
151+
; CHECK: %[[#f32VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_f32]]
152+
; CHECK: %[[#]] = OpAll %[[#bool]] %[[#f32VecNotEq]]
153153
%hlsl.all = call i1 @llvm.spv.all.v4f32(<4 x float> %p0)
154154
ret i1 %hlsl.all
155155
}
156156

157157
define noundef i1 @all_double4(<4 x double> noundef %p0) {
158158
entry:
159159
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
160-
; CHECK: %[[#f64VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_f64:]]
161-
; CHECK: %[[#]] = OpAll %[[#bool:]] %[[#f64VecNotEq:]]
160+
; CHECK: %[[#f64VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_f64]]
161+
; CHECK: %[[#]] = OpAll %[[#bool]] %[[#f64VecNotEq]]
162162
%hlsl.all = call i1 @llvm.spv.all.v4f64(<4 x double> %p0)
163163
ret i1 %hlsl.all
164164
}
165165

166166
define noundef i1 @all_bool(i1 noundef %a) {
167167
entry:
168-
; CHECK: %[[#all_bool_arg:]] = OpFunctionParameter %[[#bool:]]
169-
; CHECK: OpReturnValue %[[#all_bool_arg:]]
168+
; CHECK: %[[#all_bool_arg:]] = OpFunctionParameter %[[#bool]]
169+
; CHECK: OpReturnValue %[[#all_bool_arg]]
170170
%hlsl.all = call i1 @llvm.spv.all.i1(i1 %a)
171171
ret i1 %hlsl.all
172172
}

‎llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll

Lines changed: 38 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -26,32 +26,32 @@
2626
; CHECK-HLSL-DAG: %[[#const_i32_0:]] = OpConstant %[[#int_32]] 0
2727
; CHECK-HLSL-DAG: %[[#const_i16_0:]] = OpConstant %[[#int_16]] 0
2828
; CHECK-HLSL-DAG: %[[#const_f64_0:]] = OpConstant %[[#float_64]] 0
29-
; CHECK-HLSL-DAG: %[[#const_f32_0:]] = OpConstant %[[#float_32:]] 0
30-
; CHECK-HLSL-DAG: %[[#const_f16_0:]] = OpConstant %[[#float_16:]] 0
31-
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i16:]] = OpConstantComposite %[[#vec4_16:]] %[[#const_i16_0:]] %[[#const_i16_0:]] %[[#const_i16_0:]] %[[#const_i16_0:]]
32-
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i32:]] = OpConstantComposite %[[#vec4_32:]] %[[#const_i32_0:]] %[[#const_i32_0:]] %[[#const_i32_0:]] %[[#const_i32_0:]]
33-
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i64:]] = OpConstantComposite %[[#vec4_64:]] %[[#const_i64_0:]] %[[#const_i64_0:]] %[[#const_i64_0:]] %[[#const_i64_0:]]
34-
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f16:]] = OpConstantComposite %[[#vec4_float_16:]] %[[#const_f16_0:]] %[[#const_f16_0:]] %[[#const_f16_0:]] %[[#const_f16_0:]]
35-
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f32:]] = OpConstantComposite %[[#vec4_float_32:]] %[[#const_f32_0:]] %[[#const_f32_0:]] %[[#const_f32_0:]] %[[#const_f32_0:]]
36-
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f64:]] = OpConstantComposite %[[#vec4_float_64:]] %[[#const_f64_0:]] %[[#const_f64_0:]] %[[#const_f64_0:]] %[[#const_f64_0:]]
29+
; CHECK-HLSL-DAG: %[[#const_f32_0:]] = OpConstant %[[#float_32]] 0
30+
; CHECK-HLSL-DAG: %[[#const_f16_0:]] = OpConstant %[[#float_16]] 0
31+
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i16:]] = OpConstantComposite %[[#vec4_16]] %[[#const_i16_0]] %[[#const_i16_0]] %[[#const_i16_0]] %[[#const_i16_0]]
32+
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i32:]] = OpConstantComposite %[[#vec4_32]] %[[#const_i32_0]] %[[#const_i32_0]] %[[#const_i32_0]] %[[#const_i32_0]]
33+
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i64:]] = OpConstantComposite %[[#vec4_64]] %[[#const_i64_0]] %[[#const_i64_0]] %[[#const_i64_0]] %[[#const_i64_0]]
34+
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f16:]] = OpConstantComposite %[[#vec4_float_16]] %[[#const_f16_0]] %[[#const_f16_0]] %[[#const_f16_0]] %[[#const_f16_0]]
35+
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f32:]] = OpConstantComposite %[[#vec4_float_32]] %[[#const_f32_0]] %[[#const_f32_0]] %[[#const_f32_0]] %[[#const_f32_0]]
36+
; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f64:]] = OpConstantComposite %[[#vec4_float_64]] %[[#const_f64_0]] %[[#const_f64_0]] %[[#const_f64_0]] %[[#const_f64_0]]
3737

3838
; CHECK-OCL-DAG: %[[#const_i64_0:]] = OpConstantNull %[[#int_64]]
3939
; CHECK-OCL-DAG: %[[#const_i32_0:]] = OpConstantNull %[[#int_32]]
4040
; CHECK-OCL-DAG: %[[#const_i16_0:]] = OpConstantNull %[[#int_16]]
4141
; CHECK-OCL-DAG: %[[#const_f64_0:]] = OpConstantNull %[[#float_64]]
42-
; CHECK-OCL-DAG: %[[#const_f32_0:]] = OpConstantNull %[[#float_32:]]
43-
; CHECK-OCL-DAG: %[[#const_f16_0:]] = OpConstantNull %[[#float_16:]]
44-
; CHECK-OCL-DAG: %[[#vec4_const_zeros_i16:]] = OpConstantNull %[[#vec4_16:]]
45-
; CHECK-OCL-DAG: %[[#vec4_const_zeros_i32:]] = OpConstantNull %[[#vec4_32:]]
46-
; CHECK-OCL-DAG: %[[#vec4_const_zeros_i64:]] = OpConstantNull %[[#vec4_64:]]
47-
; CHECK-OCL-DAG: %[[#vec4_const_zeros_f16:]] = OpConstantNull %[[#vec4_float_16:]]
48-
; CHECK-OCL-DAG: %[[#vec4_const_zeros_f32:]] = OpConstantNull %[[#vec4_float_32:]]
49-
; CHECK-OCL-DAG: %[[#vec4_const_zeros_f64:]] = OpConstantNull %[[#vec4_float_64:]]
42+
; CHECK-OCL-DAG: %[[#const_f32_0:]] = OpConstantNull %[[#float_32]]
43+
; CHECK-OCL-DAG: %[[#const_f16_0:]] = OpConstantNull %[[#float_16]]
44+
; CHECK-OCL-DAG: %[[#vec4_const_zeros_i16:]] = OpConstantNull %[[#vec4_16]]
45+
; CHECK-OCL-DAG: %[[#vec4_const_zeros_i32:]] = OpConstantNull %[[#vec4_32]]
46+
; CHECK-OCL-DAG: %[[#vec4_const_zeros_i64:]] = OpConstantNull %[[#vec4_64]]
47+
; CHECK-OCL-DAG: %[[#vec4_const_zeros_f16:]] = OpConstantNull %[[#vec4_float_16]]
48+
; CHECK-OCL-DAG: %[[#vec4_const_zeros_f32:]] = OpConstantNull %[[#vec4_float_32]]
49+
; CHECK-OCL-DAG: %[[#vec4_const_zeros_f64:]] = OpConstantNull %[[#vec4_float_64]]
5050

5151
define noundef i1 @any_int64_t(i64 noundef %p0) {
5252
entry:
5353
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
54-
; CHECK: %[[#]] = OpINotEqual %[[#bool:]] %[[#arg0:]] %[[#const_i64_0:]]
54+
; CHECK: %[[#]] = OpINotEqual %[[#bool]] %[[#arg0]] %[[#const_i64_0]]
5555
%hlsl.any = call i1 @llvm.spv.any.i64(i64 %p0)
5656
ret i1 %hlsl.any
5757
}
@@ -60,7 +60,7 @@ entry:
6060
define noundef i1 @any_int(i32 noundef %p0) {
6161
entry:
6262
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
63-
; CHECK: %[[#]] = OpINotEqual %[[#bool:]] %[[#arg0:]] %[[#const_i32_0:]]
63+
; CHECK: %[[#]] = OpINotEqual %[[#bool]] %[[#arg0]] %[[#const_i32_0]]
6464
%hlsl.any = call i1 @llvm.spv.any.i32(i32 %p0)
6565
ret i1 %hlsl.any
6666
}
@@ -69,15 +69,15 @@ entry:
6969
define noundef i1 @any_int16_t(i16 noundef %p0) {
7070
entry:
7171
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
72-
; CHECK: %[[#]] = OpINotEqual %[[#bool:]] %[[#arg0:]] %[[#const_i16_0:]]
72+
; CHECK: %[[#]] = OpINotEqual %[[#bool]] %[[#arg0]] %[[#const_i16_0]]
7373
%hlsl.any = call i1 @llvm.spv.any.i16(i16 %p0)
7474
ret i1 %hlsl.any
7575
}
7676

7777
define noundef i1 @any_double(double noundef %p0) {
7878
entry:
7979
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
80-
; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool:]] %[[#arg0:]] %[[#const_f64_0:]]
80+
; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool]] %[[#arg0]] %[[#const_f64_0]]
8181
%hlsl.any = call i1 @llvm.spv.any.f64(double %p0)
8282
ret i1 %hlsl.any
8383
}
@@ -86,7 +86,7 @@ entry:
8686
define noundef i1 @any_float(float noundef %p0) {
8787
entry:
8888
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
89-
; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool:]] %[[#arg0:]] %[[#const_f32_0:]]
89+
; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool]] %[[#arg0]] %[[#const_f32_0]]
9090
%hlsl.any = call i1 @llvm.spv.any.f32(float %p0)
9191
ret i1 %hlsl.any
9292
}
@@ -95,78 +95,78 @@ entry:
9595
define noundef i1 @any_half(half noundef %p0) {
9696
entry:
9797
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
98-
; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool:]] %[[#arg0:]] %[[#const_f16_0:]]
98+
; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool]] %[[#arg0]] %[[#const_f16_0]]
9999
%hlsl.any = call i1 @llvm.spv.any.f16(half %p0)
100100
ret i1 %hlsl.any
101101
}
102102

103103

104104
define noundef i1 @any_bool4(<4 x i1> noundef %p0) {
105105
entry:
106-
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
107-
; CHECK: %[[#]] = OpAny %[[#vec4_bool:]] %[[#arg0:]]
106+
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec4_bool]]
107+
; CHECK: %[[#]] = OpAny %[[#bool]] %[[#arg0]]
108108
%hlsl.any = call i1 @llvm.spv.any.v4i1(<4 x i1> %p0)
109109
ret i1 %hlsl.any
110110
}
111111

112112
define noundef i1 @any_short4(<4 x i16> noundef %p0) {
113113
entry:
114114
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
115-
; CHECK: %[[#shortVecNotEq:]] = OpINotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_i16:]]
116-
; CHECK: %[[#]] = OpAny %[[#bool:]] %[[#shortVecNotEq:]]
115+
; CHECK: %[[#shortVecNotEq:]] = OpINotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_i16]]
116+
; CHECK: %[[#]] = OpAny %[[#bool]] %[[#shortVecNotEq]]
117117
%hlsl.any = call i1 @llvm.spv.any.v4i16(<4 x i16> %p0)
118118
ret i1 %hlsl.any
119119
}
120120

121121
define noundef i1 @any_int4(<4 x i32> noundef %p0) {
122122
entry:
123123
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
124-
; CHECK: %[[#i32VecNotEq:]] = OpINotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_i32:]]
125-
; CHECK: %[[#]] = OpAny %[[#bool:]] %[[#i32VecNotEq:]]
124+
; CHECK: %[[#i32VecNotEq:]] = OpINotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_i32]]
125+
; CHECK: %[[#]] = OpAny %[[#bool]] %[[#i32VecNotEq]]
126126
%hlsl.any = call i1 @llvm.spv.any.v4i32(<4 x i32> %p0)
127127
ret i1 %hlsl.any
128128
}
129129

130130
define noundef i1 @any_int64_t4(<4 x i64> noundef %p0) {
131131
entry:
132132
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
133-
; CHECK: %[[#i64VecNotEq:]] = OpINotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_i64:]]
134-
; CHECK: %[[#]] = OpAny %[[#bool:]] %[[#i64VecNotEq]]
133+
; CHECK: %[[#i64VecNotEq:]] = OpINotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_i64]]
134+
; CHECK: %[[#]] = OpAny %[[#bool]] %[[#i64VecNotEq]]
135135
%hlsl.any = call i1 @llvm.spv.any.v4i64(<4 x i64> %p0)
136136
ret i1 %hlsl.any
137137
}
138138

139139
define noundef i1 @any_half4(<4 x half> noundef %p0) {
140140
entry:
141141
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
142-
; CHECK: %[[#f16VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_f16:]]
143-
; CHECK: %[[#]] = OpAny %[[#bool]] %[[#f16VecNotEq:]]
142+
; CHECK: %[[#f16VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_f16]]
143+
; CHECK: %[[#]] = OpAny %[[#bool]] %[[#f16VecNotEq]]
144144
%hlsl.any = call i1 @llvm.spv.any.v4f16(<4 x half> %p0)
145145
ret i1 %hlsl.any
146146
}
147147

148148
define noundef i1 @any_float4(<4 x float> noundef %p0) {
149149
entry:
150150
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
151-
; CHECK: %[[#f32VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_f32:]]
152-
; CHECK: %[[#]] = OpAny %[[#bool:]] %[[#f32VecNotEq:]]
151+
; CHECK: %[[#f32VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_f32]]
152+
; CHECK: %[[#]] = OpAny %[[#bool]] %[[#f32VecNotEq]]
153153
%hlsl.any = call i1 @llvm.spv.any.v4f32(<4 x float> %p0)
154154
ret i1 %hlsl.any
155155
}
156156

157157
define noundef i1 @any_double4(<4 x double> noundef %p0) {
158158
entry:
159159
; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
160-
; CHECK: %[[#f64VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_f64:]]
161-
; CHECK: %[[#]] = OpAny %[[#bool:]] %[[#f64VecNotEq:]]
160+
; CHECK: %[[#f64VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool]] %[[#arg0]] %[[#vec4_const_zeros_f64]]
161+
; CHECK: %[[#]] = OpAny %[[#bool]] %[[#f64VecNotEq]]
162162
%hlsl.any = call i1 @llvm.spv.any.v4f64(<4 x double> %p0)
163163
ret i1 %hlsl.any
164164
}
165165

166166
define noundef i1 @any_bool(i1 noundef %a) {
167167
entry:
168-
; CHECK: %[[#any_bool_arg:]] = OpFunctionParameter %[[#bool:]]
169-
; CHECK: OpReturnValue %[[#any_bool_arg:]]
168+
; CHECK: %[[#any_bool_arg:]] = OpFunctionParameter %[[#bool]]
169+
; CHECK: OpReturnValue %[[#any_bool_arg]]
170170
%hlsl.any = call i1 @llvm.spv.any.i1(i1 %a)
171171
ret i1 %hlsl.any
172172
}

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