@@ -1243,6 +1243,7 @@ struct AdditionalKeywords {
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kw_unique0 = &IdentTable.get (" unique0" );
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kw_uwire = &IdentTable.get (" uwire" );
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kw_vectored = &IdentTable.get (" vectored" );
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+ kw_wait = &IdentTable.get (" wait" );
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kw_wand = &IdentTable.get (" wand" );
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kw_weak0 = &IdentTable.get (" weak0" );
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kw_weak1 = &IdentTable.get (" weak1" );
@@ -1299,70 +1300,49 @@ struct AdditionalKeywords {
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// treatment like `showcancelled` or they should be treated as identifiers
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// like `int` and `logic`.
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VerilogExtraKeywords = std::unordered_set<IdentifierInfo *>(
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- {kw_always, kw_always_comb,
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- kw_always_ff, kw_always_latch,
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- kw_assert, kw_assign,
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- kw_assume, kw_automatic,
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- kw_before, kw_begin,
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- kw_bins, kw_binsof,
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- kw_casex, kw_casez,
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- kw_celldefine, kw_checker,
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- kw_clocking, kw_constraint,
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- kw_cover, kw_covergroup,
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- kw_coverpoint, kw_disable,
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- kw_dist, kw_edge,
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- kw_end, kw_endcase,
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- kw_endchecker, kw_endclass,
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- kw_endclocking, kw_endfunction,
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- kw_endgenerate, kw_endgroup,
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- kw_endinterface, kw_endmodule,
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- kw_endpackage, kw_endprimitive,
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- kw_endprogram, kw_endproperty,
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- kw_endsequence, kw_endspecify,
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- kw_endtable, kw_endtask,
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- kw_extends, kw_final,
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- kw_foreach, kw_forever,
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- kw_fork, kw_function,
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- kw_generate, kw_highz0,
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- kw_highz1, kw_iff,
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- kw_ifnone, kw_ignore_bins,
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- kw_illegal_bins, kw_implements,
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- kw_import, kw_initial,
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- kw_inout, kw_input,
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- kw_inside, kw_interconnect,
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- kw_interface, kw_intersect,
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- kw_join, kw_join_any,
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- kw_join_none, kw_large,
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- kw_let, kw_local,
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- kw_localparam, kw_macromodule,
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- kw_matches, kw_medium,
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- kw_negedge, kw_output,
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- kw_package, kw_packed,
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- kw_parameter, kw_posedge,
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- kw_primitive, kw_priority,
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- kw_program, kw_property,
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- kw_pull0, kw_pull1,
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- kw_pure, kw_rand,
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- kw_randc, kw_randcase,
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- kw_randsequence, kw_ref,
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- kw_repeat, kw_sample,
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- kw_scalared, kw_sequence,
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- kw_small, kw_soft,
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- kw_solve, kw_specify,
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- kw_specparam, kw_strong0,
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- kw_strong1, kw_supply0,
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- kw_supply1, kw_table,
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- kw_tagged, kw_task,
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- kw_tri, kw_tri0,
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- kw_tri1, kw_triand,
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- kw_trior, kw_trireg,
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- kw_unique, kw_unique0,
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- kw_uwire, kw_var,
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- kw_vectored, kw_wand,
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- kw_weak0, kw_weak1,
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- kw_wildcard, kw_wire,
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- kw_with, kw_wor,
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- kw_verilogHash, kw_verilogHashHash});
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+ {kw_always, kw_always_comb, kw_always_ff,
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+ kw_always_latch, kw_assert, kw_assign,
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+ kw_assume, kw_automatic, kw_before,
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+ kw_begin, kw_bins, kw_binsof,
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+ kw_casex, kw_casez, kw_celldefine,
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+ kw_checker, kw_clocking, kw_constraint,
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+ kw_cover, kw_covergroup, kw_coverpoint,
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+ kw_disable, kw_dist, kw_edge,
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+ kw_end, kw_endcase, kw_endchecker,
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+ kw_endclass, kw_endclocking, kw_endfunction,
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+ kw_endgenerate, kw_endgroup, kw_endinterface,
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+ kw_endmodule, kw_endpackage, kw_endprimitive,
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+ kw_endprogram, kw_endproperty, kw_endsequence,
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+ kw_endspecify, kw_endtable, kw_endtask,
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+ kw_extends, kw_final, kw_foreach,
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+ kw_forever, kw_fork, kw_function,
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+ kw_generate, kw_highz0, kw_highz1,
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+ kw_iff, kw_ifnone, kw_ignore_bins,
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+ kw_illegal_bins, kw_implements, kw_import,
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+ kw_initial, kw_inout, kw_input,
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+ kw_inside, kw_interconnect, kw_interface,
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+ kw_intersect, kw_join, kw_join_any,
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+ kw_join_none, kw_large, kw_let,
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+ kw_local, kw_localparam, kw_macromodule,
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+ kw_matches, kw_medium, kw_negedge,
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+ kw_output, kw_package, kw_packed,
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+ kw_parameter, kw_posedge, kw_primitive,
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+ kw_priority, kw_program, kw_property,
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+ kw_pull0, kw_pull1, kw_pure,
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+ kw_rand, kw_randc, kw_randcase,
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+ kw_randsequence, kw_ref, kw_repeat,
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+ kw_sample, kw_scalared, kw_sequence,
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+ kw_small, kw_soft, kw_solve,
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+ kw_specify, kw_specparam, kw_strong0,
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+ kw_strong1, kw_supply0, kw_supply1,
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+ kw_table, kw_tagged, kw_task,
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+ kw_tri, kw_tri0, kw_tri1,
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+ kw_triand, kw_trior, kw_trireg,
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+ kw_unique, kw_unique0, kw_uwire,
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+ kw_var, kw_vectored, kw_wait,
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+ kw_wand, kw_weak0, kw_weak1,
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+ kw_wildcard, kw_wire, kw_with,
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+ kw_wor, kw_verilogHash, kw_verilogHashHash});
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TableGenExtraKeywords = std::unordered_set<IdentifierInfo *>({
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kw_assert,
@@ -1614,6 +1594,7 @@ struct AdditionalKeywords {
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IdentifierInfo *kw_unique0;
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IdentifierInfo *kw_uwire;
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IdentifierInfo *kw_vectored;
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+ IdentifierInfo *kw_wait;
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IdentifierInfo *kw_wand;
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IdentifierInfo *kw_weak0;
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IdentifierInfo *kw_weak1;
@@ -1849,8 +1830,12 @@ struct AdditionalKeywords {
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// / Returns whether \p Tok is a Verilog keyword that opens a block.
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bool isVerilogBegin (const FormatToken &Tok) const {
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// `table` is not included since it needs to be treated specially.
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- return !Tok.endsSequence (kw_fork, kw_disable) &&
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- Tok.isOneOf (kw_begin, kw_fork, kw_generate, kw_specify);
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+ if (Tok.isOneOf (kw_begin, kw_generate, kw_specify))
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+ return true ;
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+ if (Tok.isNot (kw_fork))
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+ return false ;
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+ const auto *Prev = Tok.getPreviousNonComment ();
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+ return !(Prev && Prev->isOneOf (kw_disable, kw_wait));
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}
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// / Returns whether \p Tok is a Verilog keyword that closes a block.
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