Skip to content

Commit cbb4621

Browse files
[SelectionDAG] Expand @llvm.copysign.ppc_fp128 without copysignl
1 parent 9169c5f commit cbb4621

File tree

1 file changed

+12
-5
lines changed

1 file changed

+12
-5
lines changed

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1710,11 +1710,18 @@ void DAGTypeLegalizer::ExpandFloatRes_FCEIL(SDNode *N,
17101710
void DAGTypeLegalizer::ExpandFloatRes_FCOPYSIGN(SDNode *N,
17111711
SDValue &Lo, SDValue &Hi) {
17121712

1713-
EVT VT = N->getValueType(0);
1714-
ExpandFloatRes_Binary(
1715-
N,
1716-
(VT == MVT::ppcf128 ? RTLIB::COPYSIGN_PPCF128 : RTLIB::UNKNOWN_LIBCALL),
1717-
Lo, Hi);
1713+
assert(N->getValueType(0) == MVT::ppcf128 &&
1714+
"Logic only correct for ppcf128!");
1715+
SDLoc DL = SDLoc(N);
1716+
SDValue Tmp = SDValue();
1717+
GetExpandedFloat(N->getOperand(0), Lo, Tmp);
1718+
1719+
Hi = DAG.getNode(ISD::FCOPYSIGN, DL, Tmp.getValueType(), Tmp,
1720+
N->getOperand(1));
1721+
// A double-double is Hi + Lo, so if Hi flips sign, so must Lo
1722+
Lo = DAG.getSelectCC(DL, Tmp, Hi, Lo,
1723+
DAG.getNode(ISD::FNEG, DL, Lo.getValueType(), Lo),
1724+
ISD::SETEQ);
17181725
}
17191726

17201727
void DAGTypeLegalizer::ExpandFloatRes_FCOS(SDNode *N,

0 commit comments

Comments
 (0)