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Add coverage for missing (urem x, (lshr pow2, y)) -> (and x, (add (lshr pow2, y), -1)) transform
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‎llvm/test/CodeGen/X86/combine-urem.ll

Lines changed: 213 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -357,6 +357,219 @@ define <4 x i32> @combine_vec_urem_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {
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ret <4 x i32> %2
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}
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; fold (urem x, (lshr pow2, y)) -> (and x, (add (lshr pow2, y), -1))
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define <4 x i32> @combine_vec_urem_by_lshr_pow2a(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_urem_by_lshr_pow2a:
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; SSE: # %bb.0:
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; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
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; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm3[2,3,3,3,4,5,6,7]
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; SSE-NEXT: movdqa {{.*#+}} xmm5 = [4,4,4,4]
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; SSE-NEXT: movdqa %xmm5, %xmm2
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; SSE-NEXT: psrld %xmm4, %xmm2
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; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,1,1,4,5,6,7]
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; SSE-NEXT: movdqa %xmm5, %xmm4
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; SSE-NEXT: psrld %xmm3, %xmm4
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; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[0,1,1,1,4,5,6,7]
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; SSE-NEXT: movdqa %xmm5, %xmm6
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; SSE-NEXT: psrld %xmm3, %xmm6
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; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[2,3,3,3,4,5,6,7]
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; SSE-NEXT: psrld %xmm1, %xmm5
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; SSE-NEXT: pextrd $1, %xmm5, %ecx
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; SSE-NEXT: pextrd $1, %xmm0, %eax
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %ecx
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; SSE-NEXT: movl %edx, %ecx
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; SSE-NEXT: movd %xmm6, %esi
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; SSE-NEXT: movd %xmm0, %eax
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %esi
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; SSE-NEXT: movd %edx, %xmm1
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; SSE-NEXT: pinsrd $1, %ecx, %xmm1
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; SSE-NEXT: pextrd $2, %xmm4, %ecx
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; SSE-NEXT: pextrd $2, %xmm0, %eax
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %ecx
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; SSE-NEXT: pinsrd $2, %edx, %xmm1
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; SSE-NEXT: pextrd $3, %xmm2, %ecx
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; SSE-NEXT: pextrd $3, %xmm0, %eax
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %ecx
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; SSE-NEXT: pinsrd $3, %edx, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_urem_by_lshr_pow2a:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [4,4,4,4]
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; AVX1-NEXT: vpsrld %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
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; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm4 = xmm1[2],xmm4[2],xmm1[3],xmm4[3]
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; AVX1-NEXT: vpsrld %xmm4, %xmm3, %xmm4
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; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm1[0],zero,xmm1[1],zero
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; AVX1-NEXT: vpsrld %xmm5, %xmm3, %xmm5
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; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm1
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; AVX1-NEXT: vpsrld %xmm1, %xmm3, %xmm1
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; AVX1-NEXT: vpextrd $1, %xmm1, %ecx
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; AVX1-NEXT: vpextrd $1, %xmm0, %eax
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; AVX1-NEXT: xorl %edx, %edx
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; AVX1-NEXT: divl %ecx
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; AVX1-NEXT: movl %edx, %ecx
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; AVX1-NEXT: vmovd %xmm5, %esi
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; AVX1-NEXT: vmovd %xmm0, %eax
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; AVX1-NEXT: xorl %edx, %edx
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; AVX1-NEXT: divl %esi
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; AVX1-NEXT: vmovd %edx, %xmm1
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; AVX1-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
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; AVX1-NEXT: vpextrd $2, %xmm4, %ecx
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; AVX1-NEXT: vpextrd $2, %xmm0, %eax
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; AVX1-NEXT: xorl %edx, %edx
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; AVX1-NEXT: divl %ecx
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; AVX1-NEXT: vpinsrd $2, %edx, %xmm1, %xmm1
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; AVX1-NEXT: vpextrd $3, %xmm2, %ecx
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; AVX1-NEXT: vpextrd $3, %xmm0, %eax
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; AVX1-NEXT: xorl %edx, %edx
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; AVX1-NEXT: divl %ecx
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; AVX1-NEXT: vpinsrd $3, %edx, %xmm1, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_urem_by_lshr_pow2a:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [4,4,4,4]
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; AVX2-NEXT: vpsrlvd %xmm1, %xmm2, %xmm1
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; AVX2-NEXT: vpextrd $1, %xmm1, %ecx
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; AVX2-NEXT: vpextrd $1, %xmm0, %eax
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; AVX2-NEXT: xorl %edx, %edx
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; AVX2-NEXT: divl %ecx
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; AVX2-NEXT: movl %edx, %ecx
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; AVX2-NEXT: vmovd %xmm1, %esi
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; AVX2-NEXT: vmovd %xmm0, %eax
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; AVX2-NEXT: xorl %edx, %edx
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; AVX2-NEXT: divl %esi
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; AVX2-NEXT: vmovd %edx, %xmm2
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; AVX2-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
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; AVX2-NEXT: vpextrd $2, %xmm1, %ecx
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; AVX2-NEXT: vpextrd $2, %xmm0, %eax
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; AVX2-NEXT: xorl %edx, %edx
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; AVX2-NEXT: divl %ecx
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; AVX2-NEXT: vpinsrd $2, %edx, %xmm2, %xmm2
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; AVX2-NEXT: vpextrd $3, %xmm1, %ecx
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; AVX2-NEXT: vpextrd $3, %xmm0, %eax
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; AVX2-NEXT: xorl %edx, %edx
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; AVX2-NEXT: divl %ecx
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; AVX2-NEXT: vpinsrd $3, %edx, %xmm2, %xmm0
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; AVX2-NEXT: retq
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%1 = lshr <4 x i32> <i32 4, i32 4, i32 4, i32 4>, %y
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%2 = urem <4 x i32> %x, %1
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_urem_by_lshr_pow2b(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: combine_vec_urem_by_lshr_pow2b:
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; SSE: # %bb.0:
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; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
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; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm3[2,3,3,3,4,5,6,7]
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; SSE-NEXT: movdqa {{.*#+}} xmm5 = [1,4,8,16]
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; SSE-NEXT: movdqa %xmm5, %xmm2
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; SSE-NEXT: psrld %xmm4, %xmm2
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; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,1,1,4,5,6,7]
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; SSE-NEXT: movdqa %xmm5, %xmm4
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; SSE-NEXT: psrld %xmm3, %xmm4
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; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[0,1,1,1,4,5,6,7]
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; SSE-NEXT: movdqa %xmm5, %xmm6
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; SSE-NEXT: psrld %xmm3, %xmm6
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; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[2,3,3,3,4,5,6,7]
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; SSE-NEXT: psrld %xmm1, %xmm5
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; SSE-NEXT: pextrd $1, %xmm5, %ecx
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; SSE-NEXT: pextrd $1, %xmm0, %eax
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %ecx
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; SSE-NEXT: movl %edx, %ecx
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; SSE-NEXT: movd %xmm6, %esi
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; SSE-NEXT: movd %xmm0, %eax
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %esi
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; SSE-NEXT: movd %edx, %xmm1
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; SSE-NEXT: pinsrd $1, %ecx, %xmm1
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; SSE-NEXT: pextrd $2, %xmm4, %ecx
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; SSE-NEXT: pextrd $2, %xmm0, %eax
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %ecx
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; SSE-NEXT: pinsrd $2, %edx, %xmm1
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; SSE-NEXT: pextrd $3, %xmm2, %ecx
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; SSE-NEXT: pextrd $3, %xmm0, %eax
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; SSE-NEXT: xorl %edx, %edx
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; SSE-NEXT: divl %ecx
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; SSE-NEXT: pinsrd $3, %edx, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_urem_by_lshr_pow2b:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,4,8,16]
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; AVX1-NEXT: vpsrld %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
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; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm4 = xmm1[2],xmm4[2],xmm1[3],xmm4[3]
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; AVX1-NEXT: vpsrld %xmm4, %xmm3, %xmm4
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; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm1[0],zero,xmm1[1],zero
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; AVX1-NEXT: vpsrld %xmm5, %xmm3, %xmm5
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; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm1
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; AVX1-NEXT: vpsrld %xmm1, %xmm3, %xmm1
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; AVX1-NEXT: vpextrd $1, %xmm1, %ecx
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; AVX1-NEXT: vpextrd $1, %xmm0, %eax
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; AVX1-NEXT: xorl %edx, %edx
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; AVX1-NEXT: divl %ecx
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; AVX1-NEXT: movl %edx, %ecx
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; AVX1-NEXT: vmovd %xmm5, %esi
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; AVX1-NEXT: vmovd %xmm0, %eax
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; AVX1-NEXT: xorl %edx, %edx
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; AVX1-NEXT: divl %esi
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; AVX1-NEXT: vmovd %edx, %xmm1
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; AVX1-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
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; AVX1-NEXT: vpextrd $2, %xmm4, %ecx
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; AVX1-NEXT: vpextrd $2, %xmm0, %eax
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; AVX1-NEXT: xorl %edx, %edx
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; AVX1-NEXT: divl %ecx
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; AVX1-NEXT: vpinsrd $2, %edx, %xmm1, %xmm1
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; AVX1-NEXT: vpextrd $3, %xmm2, %ecx
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; AVX1-NEXT: vpextrd $3, %xmm0, %eax
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; AVX1-NEXT: xorl %edx, %edx
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; AVX1-NEXT: divl %ecx
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; AVX1-NEXT: vpinsrd $3, %edx, %xmm1, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_urem_by_lshr_pow2b:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [1,4,8,16]
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; AVX2-NEXT: vpsrlvd %xmm1, %xmm2, %xmm1
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; AVX2-NEXT: vpextrd $1, %xmm1, %ecx
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; AVX2-NEXT: vpextrd $1, %xmm0, %eax
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; AVX2-NEXT: xorl %edx, %edx
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; AVX2-NEXT: divl %ecx
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; AVX2-NEXT: movl %edx, %ecx
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; AVX2-NEXT: vmovd %xmm1, %esi
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; AVX2-NEXT: vmovd %xmm0, %eax
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; AVX2-NEXT: xorl %edx, %edx
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; AVX2-NEXT: divl %esi
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; AVX2-NEXT: vmovd %edx, %xmm2
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; AVX2-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
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; AVX2-NEXT: vpextrd $2, %xmm1, %ecx
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; AVX2-NEXT: vpextrd $2, %xmm0, %eax
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; AVX2-NEXT: xorl %edx, %edx
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; AVX2-NEXT: divl %ecx
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; AVX2-NEXT: vpinsrd $2, %edx, %xmm2, %xmm2
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; AVX2-NEXT: vpextrd $3, %xmm1, %ecx
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; AVX2-NEXT: vpextrd $3, %xmm0, %eax
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; AVX2-NEXT: xorl %edx, %edx
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; AVX2-NEXT: divl %ecx
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; AVX2-NEXT: vpinsrd $3, %edx, %xmm2, %xmm0
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; AVX2-NEXT: retq
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%1 = lshr <4 x i32> <i32 1, i32 4, i32 8, i32 16>, %y
569+
%2 = urem <4 x i32> %x, %1
570+
ret <4 x i32> %2
571+
}
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360573
; FIXME: PR55271 - urem(undef, 3) != undef
361574
; Use PSLLI intrinsic to postpone the undef creation until after urem-by-constant expansion
362575
define <4 x i32> @combine_vec_urem_undef_by_3(<4 x i32> %in) {

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