[SLP][NFC]Add a test with potential alternate node, marked for minbitwidth size

Author: alexey-bataev

llvm/test/Transforms/SLPVectorizer/AArch64/alternate-vectorization-split-node.ll

@@ -0,0 +1,57 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S --passes=slp-vectorizer -slp-threshold=-100 -mtriple=arm64-apple-macosx13.0.0 < %s | FileCheck %s
+
+define i32 @test(ptr %c) {
+; CHECK-LABEL: define i32 @test(
+; CHECK-SAME: ptr [[C:%.*]]) {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[BITLEN:%.*]] = getelementptr i8, ptr [[C]], i64 136
+; CHECK-NEXT:    [[INCDEC_PTR_3_1:%.*]] = getelementptr i8, ptr [[C]], i64 115
+; CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i64>, ptr [[BITLEN]], align 8
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> poison, <6 x i32> <i32 1, i32 1, i32 1, i32 1, i32 0, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = lshr <6 x i64> [[TMP1]], zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> poison, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 1, i32 0, i32 poison, i32 poison>
+; CHECK-NEXT:    [[TMP4:%.*]] = call <8 x i64> @llvm.vector.insert.v8i64.v6i64(<8 x i64> poison, <6 x i64> [[TMP2]], i64 0)
+; CHECK-NEXT:    [[TMP5:%.*]] = shufflevector <8 x i64> [[TMP4]], <8 x i64> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 4, i32 5>
+; CHECK-NEXT:    [[TMP6:%.*]] = trunc <8 x i64> [[TMP5]] to <8 x i8>
+; CHECK-NEXT:    store <8 x i8> [[TMP6]], ptr [[INCDEC_PTR_3_1]], align 1
+; CHECK-NEXT:    ret i32 0
+;
+entry:
+  %bitlen = getelementptr i8, ptr %c, i64 136
+  %0 = load i64, ptr %bitlen, align 8
+  %incdec.ptr.4 = getelementptr i8, ptr %c, i64 122
+  %shr45.4 = lshr i64 %0, 0
+  %conv43.5 = trunc i64 %shr45.4 to i8
+  %incdec.ptr.5 = getelementptr i8, ptr %c, i64 121
+  store i8 %conv43.5, ptr %incdec.ptr.4, align 1
+  %shr45.5 = lshr i64 %0, 0
+  %conv43.6 = trunc i64 %shr45.5 to i8
+  %incdec.ptr.6 = getelementptr i8, ptr %c, i64 120
+  store i8 %conv43.6, ptr %incdec.ptr.5, align 1
+  %conv43.7 = trunc i64 %0 to i8
+  %incdec.ptr.7 = getelementptr i8, ptr %c, i64 119
+  store i8 %conv43.7, ptr %incdec.ptr.6, align 1
+  %arrayidx38.1 = getelementptr i8, ptr %c, i64 144
+  %1 = load i64, ptr %arrayidx38.1, align 8
+  %conv43.145 = trunc i64 %1 to i8
+  %incdec.ptr.146 = getelementptr i8, ptr %c, i64 118
+  store i8 %conv43.145, ptr %incdec.ptr.7, align 1
+  %shr45.147 = lshr i64 %1, 0
+  %conv43.1.1 = trunc i64 %shr45.147 to i8
+  %incdec.ptr.1.1 = getelementptr i8, ptr %c, i64 117
+  store i8 %conv43.1.1, ptr %incdec.ptr.146, align 1
+  %shr45.1.1 = lshr i64 %1, 0
+  %conv43.2.1 = trunc i64 %shr45.1.1 to i8
+  %incdec.ptr.2.1 = getelementptr i8, ptr %c, i64 116
+  store i8 %conv43.2.1, ptr %incdec.ptr.1.1, align 1
+  %shr45.2.1 = lshr i64 %1, 0
+  %conv43.3.1 = trunc i64 %shr45.2.1 to i8
+  %incdec.ptr.3.1 = getelementptr i8, ptr %c, i64 115
+  store i8 %conv43.3.1, ptr %incdec.ptr.2.1, align 1
+  %shr45.3.1 = lshr i64 %1, 0
+  %conv43.4.1 = trunc i64 %shr45.3.1 to i8
+  store i8 %conv43.4.1, ptr %incdec.ptr.3.1, align 1
+  ret i32 0
+}
+