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[AArch64][GlobalISel] Add test coverage for reverse shuffles. NFC
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‎llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll

Lines changed: 113 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s -verify-machineinstrs | FileCheck %s
2+
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel < %s -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-GI
34

45
define <2 x i64> @v2i64(<2 x i64> %a) {
56
; CHECK-LABEL: v2i64:
@@ -12,21 +13,37 @@ entry:
1213
}
1314

1415
define <2 x ptr> @v2p0(<2 x ptr> %a) {
15-
; CHECK-LABEL: v2p0:
16-
; CHECK: // %bb.0: // %entry
17-
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
18-
; CHECK-NEXT: ret
16+
; CHECK-SD-LABEL: v2p0:
17+
; CHECK-SD: // %bb.0: // %entry
18+
; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
19+
; CHECK-SD-NEXT: ret
20+
;
21+
; CHECK-GI-LABEL: v2p0:
22+
; CHECK-GI: // %bb.0: // %entry
23+
; CHECK-GI-NEXT: adrp x8, .LCPI1_0
24+
; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1
25+
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI1_0]
26+
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
27+
; CHECK-GI-NEXT: ret
1928
entry:
2029
%V128 = shufflevector <2 x ptr> %a, <2 x ptr> undef, <2 x i32> <i32 1, i32 0>
2130
ret <2 x ptr> %V128
2231
}
2332

2433
define <4 x i32> @v4i32(<4 x i32> %a) {
25-
; CHECK-LABEL: v4i32:
26-
; CHECK: // %bb.0: // %entry
27-
; CHECK-NEXT: rev64 v0.4s, v0.4s
28-
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
29-
; CHECK-NEXT: ret
34+
; CHECK-SD-LABEL: v4i32:
35+
; CHECK-SD: // %bb.0: // %entry
36+
; CHECK-SD-NEXT: rev64 v0.4s, v0.4s
37+
; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
38+
; CHECK-SD-NEXT: ret
39+
;
40+
; CHECK-GI-LABEL: v4i32:
41+
; CHECK-GI: // %bb.0: // %entry
42+
; CHECK-GI-NEXT: adrp x8, .LCPI2_0
43+
; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1
44+
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI2_0]
45+
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
46+
; CHECK-GI-NEXT: ret
3047
entry:
3148
%V128 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
3249
ret <4 x i32> %V128
@@ -43,25 +60,42 @@ entry:
4360
}
4461

4562
define <8 x i16> @v8i16(<8 x i16> %a) {
46-
; CHECK-LABEL: v8i16:
47-
; CHECK: // %bb.0: // %entry
48-
; CHECK-NEXT: rev64 v0.8h, v0.8h
49-
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
50-
; CHECK-NEXT: ret
63+
; CHECK-SD-LABEL: v8i16:
64+
; CHECK-SD: // %bb.0: // %entry
65+
; CHECK-SD-NEXT: rev64 v0.8h, v0.8h
66+
; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
67+
; CHECK-SD-NEXT: ret
68+
;
69+
; CHECK-GI-LABEL: v8i16:
70+
; CHECK-GI: // %bb.0: // %entry
71+
; CHECK-GI-NEXT: adrp x8, .LCPI4_0
72+
; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1
73+
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI4_0]
74+
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
75+
; CHECK-GI-NEXT: ret
5176
entry:
5277
%V128 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
5378
ret <8 x i16> %V128
5479
}
5580

5681
define <8 x i16> @v8i16_2(<4 x i16> %a, <4 x i16> %b) {
57-
; CHECK-LABEL: v8i16_2:
58-
; CHECK: // %bb.0: // %entry
59-
; CHECK-NEXT: adrp x8, .LCPI5_0
60-
; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
61-
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI5_0]
62-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
63-
; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
64-
; CHECK-NEXT: ret
82+
; CHECK-SD-LABEL: v8i16_2:
83+
; CHECK-SD: // %bb.0: // %entry
84+
; CHECK-SD-NEXT: adrp x8, .LCPI5_0
85+
; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
86+
; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI5_0]
87+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
88+
; CHECK-SD-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
89+
; CHECK-SD-NEXT: ret
90+
;
91+
; CHECK-GI-LABEL: v8i16_2:
92+
; CHECK-GI: // %bb.0: // %entry
93+
; CHECK-GI-NEXT: adrp x8, .LCPI5_0
94+
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
95+
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI5_0]
96+
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
97+
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
98+
; CHECK-GI-NEXT: ret
6599
entry:
66100
%V128 = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
67101
ret <8 x i16> %V128
@@ -78,25 +112,42 @@ entry:
78112
}
79113

80114
define <16 x i8> @v16i8(<16 x i8> %a) {
81-
; CHECK-LABEL: v16i8:
82-
; CHECK: // %bb.0: // %entry
83-
; CHECK-NEXT: rev64 v0.16b, v0.16b
84-
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
85-
; CHECK-NEXT: ret
115+
; CHECK-SD-LABEL: v16i8:
116+
; CHECK-SD: // %bb.0: // %entry
117+
; CHECK-SD-NEXT: rev64 v0.16b, v0.16b
118+
; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
119+
; CHECK-SD-NEXT: ret
120+
;
121+
; CHECK-GI-LABEL: v16i8:
122+
; CHECK-GI: // %bb.0: // %entry
123+
; CHECK-GI-NEXT: adrp x8, .LCPI7_0
124+
; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1
125+
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI7_0]
126+
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
127+
; CHECK-GI-NEXT: ret
86128
entry:
87129
%V128 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
88130
ret <16 x i8> %V128
89131
}
90132

91133
define <16 x i8> @v16i8_2(<8 x i8> %a, <8 x i8> %b) {
92-
; CHECK-LABEL: v16i8_2:
93-
; CHECK: // %bb.0: // %entry
94-
; CHECK-NEXT: adrp x8, .LCPI8_0
95-
; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
96-
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI8_0]
97-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
98-
; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
99-
; CHECK-NEXT: ret
134+
; CHECK-SD-LABEL: v16i8_2:
135+
; CHECK-SD: // %bb.0: // %entry
136+
; CHECK-SD-NEXT: adrp x8, .LCPI8_0
137+
; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
138+
; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI8_0]
139+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
140+
; CHECK-SD-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
141+
; CHECK-SD-NEXT: ret
142+
;
143+
; CHECK-GI-LABEL: v16i8_2:
144+
; CHECK-GI: // %bb.0: // %entry
145+
; CHECK-GI-NEXT: adrp x8, .LCPI8_0
146+
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
147+
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI8_0]
148+
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
149+
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
150+
; CHECK-GI-NEXT: ret
100151
entry:
101152
%V128 = shufflevector <8 x i8> %a, <8 x i8> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
102153
ret <16 x i8> %V128
@@ -123,11 +174,19 @@ entry:
123174
}
124175

125176
define <4 x float> @v4f32(<4 x float> %a) {
126-
; CHECK-LABEL: v4f32:
127-
; CHECK: // %bb.0: // %entry
128-
; CHECK-NEXT: rev64 v0.4s, v0.4s
129-
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
130-
; CHECK-NEXT: ret
177+
; CHECK-SD-LABEL: v4f32:
178+
; CHECK-SD: // %bb.0: // %entry
179+
; CHECK-SD-NEXT: rev64 v0.4s, v0.4s
180+
; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
181+
; CHECK-SD-NEXT: ret
182+
;
183+
; CHECK-GI-LABEL: v4f32:
184+
; CHECK-GI: // %bb.0: // %entry
185+
; CHECK-GI-NEXT: adrp x8, .LCPI11_0
186+
; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1
187+
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI11_0]
188+
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
189+
; CHECK-GI-NEXT: ret
131190
entry:
132191
%V128 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
133192
ret <4 x float> %V128
@@ -144,11 +203,19 @@ entry:
144203
}
145204

146205
define <8 x half> @v8f16(<8 x half> %a) {
147-
; CHECK-LABEL: v8f16:
148-
; CHECK: // %bb.0: // %entry
149-
; CHECK-NEXT: rev64 v0.8h, v0.8h
150-
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
151-
; CHECK-NEXT: ret
206+
; CHECK-SD-LABEL: v8f16:
207+
; CHECK-SD: // %bb.0: // %entry
208+
; CHECK-SD-NEXT: rev64 v0.8h, v0.8h
209+
; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
210+
; CHECK-SD-NEXT: ret
211+
;
212+
; CHECK-GI-LABEL: v8f16:
213+
; CHECK-GI: // %bb.0: // %entry
214+
; CHECK-GI-NEXT: adrp x8, .LCPI13_0
215+
; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1
216+
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI13_0]
217+
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
218+
; CHECK-GI-NEXT: ret
152219
entry:
153220
%V128 = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
154221
ret <8 x half> %V128

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