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[RISCV] Select int_riscv_vsll with shift of 1 to vadd.vv.
Add might be faster than shift. We can't do this earlier without using a Freeze instruction. This is the intrinsic version of D106689. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D118013
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

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@@ -4543,6 +4543,30 @@ defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsrl", "PseudoVSRL", AllIntegerVectors,
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defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsra", "PseudoVSRA", AllIntegerVectors,
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uimm5>;
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foreach vti = AllIntegerVectors in {
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// Emit shift by 1 as an add since it might be faster.
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def : Pat<(vti.Vector (int_riscv_vsll (vti.Vector vti.RegClass:$rs1),
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(XLenVT 1), VLOpFrag)),
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(!cast<Instruction>("PseudoVADD_VV_"#vti.LMul.MX) vti.RegClass:$rs1,
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vti.RegClass:$rs1,
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GPR:$vl,
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vti.Log2SEW)>;
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def : Pat<(vti.Vector (int_riscv_vsll_mask (vti.Vector vti.RegClass:$merge),
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(vti.Vector vti.RegClass:$rs1),
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(XLenVT 1),
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(vti.Mask V0),
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VLOpFrag,
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(XLenVT timm:$policy))),
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(!cast<Instruction>("PseudoVADD_VV_"#vti.LMul.MX#"_MASK")
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vti.RegClass:$merge,
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vti.RegClass:$rs1,
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vti.RegClass:$rs1,
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(vti.Mask V0),
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GPR:$vl,
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vti.Log2SEW,
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(XLenVT timm:$policy))>;
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}
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//===----------------------------------------------------------------------===//
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// 12.7. Vector Narrowing Integer Right Shift Instructions
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//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll

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@@ -2000,6 +2000,21 @@ entry:
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ret <vscale x 1 x i8> %a
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}
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define <vscale x 1 x i8> @intrinsic_vsll_1_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
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; CHECK-LABEL: intrinsic_vsll_1_nxv1i8_nxv1i8_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
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; CHECK-NEXT: vadd.vv v8, v8, v8
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8(
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<vscale x 1 x i8> %0,
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i32 1,
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i32 %1)
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ret <vscale x 1 x i8> %a
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}
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define <vscale x 1 x i8> @intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
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; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8:
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; CHECK: # %bb.0: # %entry
@@ -2017,6 +2032,23 @@ entry:
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ret <vscale x 1 x i8> %a
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}
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define <vscale x 1 x i8> @intrinsic_vsll_mask_1_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
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; CHECK-LABEL: intrinsic_vsll_mask_1_nxv1i8_nxv1i8_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
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; CHECK-NEXT: vadd.vv v8, v9, v9, v0.t
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8(
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %1,
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i32 1,
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<vscale x 1 x i1> %2,
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i32 %3, i32 1)
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ret <vscale x 1 x i8> %a
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}
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define <vscale x 2 x i8> @intrinsic_vsll_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
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; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8:
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; CHECK: # %bb.0: # %entry

‎llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2000,6 +2000,21 @@ entry:
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ret <vscale x 1 x i8> %a
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}
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define <vscale x 1 x i8> @intrinsic_vsll_1_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
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; CHECK-LABEL: intrinsic_vsll_1_nxv1i8_nxv1i8_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
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; CHECK-NEXT: vadd.vv v8, v8, v8
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8(
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<vscale x 1 x i8> %0,
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i64 1,
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i64 %1)
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ret <vscale x 1 x i8> %a
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}
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define <vscale x 1 x i8> @intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
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; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8:
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; CHECK: # %bb.0: # %entry
@@ -2017,6 +2032,23 @@ entry:
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ret <vscale x 1 x i8> %a
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}
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define <vscale x 1 x i8> @intrinsic_vsll_mask_1_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
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; CHECK-LABEL: intrinsic_vsll_mask_1_nxv1i8_nxv1i8_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
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; CHECK-NEXT: vadd.vv v8, v9, v9, v0.t
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8(
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<vscale x 1 x i8> %0,
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<vscale x 1 x i8> %1,
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i64 1,
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<vscale x 1 x i1> %2,
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i64 %3, i64 1)
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ret <vscale x 1 x i8> %a
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}
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define <vscale x 2 x i8> @intrinsic_vsll_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
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; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8:
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; CHECK: # %bb.0: # %entry

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