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[AMDGPU][MC] Implement fft and rotate modes for ds_swizzle_b32 (#108064)
In addition to the basic mode, the ds_swizzle_b32 is supposed to support two specific modes: fft and rotate. This patch implements those two modes.
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11 files changed

+352
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lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 59 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1838,10 +1838,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
18381838
ParseStatus parseSOPPBrTarget(OperandVector &Operands);
18391839
ParseStatus parseBoolReg(OperandVector &Operands);
18401840

1841-
bool parseSwizzleOperand(int64_t &Op,
1842-
const unsigned MinVal,
1843-
const unsigned MaxVal,
1844-
const StringRef ErrMsg,
1841+
bool parseSwizzleOperand(int64_t &Op, const unsigned MinVal,
1842+
const unsigned MaxVal, const Twine &ErrMsg,
18451843
SMLoc &Loc);
18461844
bool parseSwizzleOperands(const unsigned OpNum, int64_t* Op,
18471845
const unsigned MinVal,
@@ -1855,6 +1853,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
18551853
bool parseSwizzleBroadcast(int64_t &Imm);
18561854
bool parseSwizzleSwap(int64_t &Imm);
18571855
bool parseSwizzleReverse(int64_t &Imm);
1856+
bool parseSwizzleFFT(int64_t &Imm);
1857+
bool parseSwizzleRotate(int64_t &Imm);
18581858

18591859
ParseStatus parseGPRIdxMode(OperandVector &Operands);
18601860
int64_t parseGPRIdxMacro();
@@ -7996,12 +7996,9 @@ encodeBitmaskPerm(const unsigned AndMask,
79967996
(XorMask << BITMASK_XOR_SHIFT);
79977997
}
79987998

7999-
bool
8000-
AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op,
8001-
const unsigned MinVal,
8002-
const unsigned MaxVal,
8003-
const StringRef ErrMsg,
8004-
SMLoc &Loc) {
7999+
bool AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op, const unsigned MinVal,
8000+
const unsigned MaxVal,
8001+
const Twine &ErrMsg, SMLoc &Loc) {
80058002
if (!skipToken(AsmToken::Comma, "expected a comma")) {
80068003
return false;
80078004
}
@@ -8166,6 +8163,54 @@ AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) {
81668163
return true;
81678164
}
81688165

8166+
bool AMDGPUAsmParser::parseSwizzleFFT(int64_t &Imm) {
8167+
using namespace llvm::AMDGPU::Swizzle;
8168+
8169+
if (!AMDGPU::isGFX9Plus(getSTI())) {
8170+
Error(getLoc(), "FFT mode swizzle not supported on this GPU");
8171+
return false;
8172+
}
8173+
8174+
int64_t Swizzle;
8175+
SMLoc Loc;
8176+
if (!parseSwizzleOperand(Swizzle, 0, FFT_SWIZZLE_MAX,
8177+
"FFT swizzle must be in the interval [0," +
8178+
Twine(FFT_SWIZZLE_MAX) + Twine(']'),
8179+
Loc))
8180+
return false;
8181+
8182+
Imm = FFT_MODE_ENC | Swizzle;
8183+
return true;
8184+
}
8185+
8186+
bool AMDGPUAsmParser::parseSwizzleRotate(int64_t &Imm) {
8187+
using namespace llvm::AMDGPU::Swizzle;
8188+
8189+
if (!AMDGPU::isGFX9Plus(getSTI())) {
8190+
Error(getLoc(), "Rotate mode swizzle not supported on this GPU");
8191+
return false;
8192+
}
8193+
8194+
SMLoc Loc;
8195+
int64_t Direction;
8196+
8197+
if (!parseSwizzleOperand(Direction, 0, 1,
8198+
"direction must be 0 (left) or 1 (right)", Loc))
8199+
return false;
8200+
8201+
int64_t RotateSize;
8202+
if (!parseSwizzleOperand(
8203+
RotateSize, 0, ROTATE_MAX_SIZE,
8204+
"number of threads to rotate must be in the interval [0," +
8205+
Twine(ROTATE_MAX_SIZE) + Twine(']'),
8206+
Loc))
8207+
return false;
8208+
8209+
Imm = ROTATE_MODE_ENC | (Direction << ROTATE_DIR_SHIFT) |
8210+
(RotateSize << ROTATE_SIZE_SHIFT);
8211+
return true;
8212+
}
8213+
81698214
bool
81708215
AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) {
81718216

@@ -8200,6 +8245,10 @@ AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) {
82008245
Ok = parseSwizzleSwap(Imm);
82018246
} else if (trySkipId(IdSymbolic[ID_REVERSE])) {
82028247
Ok = parseSwizzleReverse(Imm);
8248+
} else if (trySkipId(IdSymbolic[ID_FFT])) {
8249+
Ok = parseSwizzleFFT(Imm);
8250+
} else if (trySkipId(IdSymbolic[ID_ROTATE])) {
8251+
Ok = parseSwizzleRotate(Imm);
82038252
} else {
82048253
Error(ModeLoc, "expected a swizzle mode");
82058254
}

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1503,8 +1503,21 @@ void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
15031503

15041504
O << " offset:";
15051505

1506-
if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1506+
// Rotate and FFT modes
1507+
if (Imm >= ROTATE_MODE_LO && AMDGPU::isGFX9Plus(STI)) {
1508+
if (Imm >= FFT_MODE_LO) {
1509+
O << "swizzle(" << IdSymbolic[ID_FFT] << ',' << (Imm & FFT_SWIZZLE_MASK)
1510+
<< ')';
1511+
} else if (Imm >= ROTATE_MODE_LO) {
1512+
O << "swizzle(" << IdSymbolic[ID_ROTATE] << ','
1513+
<< ((Imm >> ROTATE_DIR_SHIFT) & ROTATE_DIR_MASK) << ','
1514+
<< ((Imm >> ROTATE_SIZE_SHIFT) & ROTATE_SIZE_MASK) << ')';
1515+
}
1516+
return;
1517+
}
15071518

1519+
// Basic mode
1520+
if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
15081521
O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
15091522
for (unsigned I = 0; I < LANE_NUM; ++I) {
15101523
O << ",";

‎llvm/lib/Target/AMDGPU/SIDefines.h

Lines changed: 26 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -841,9 +841,12 @@ enum Id : unsigned { // id of symbolic names
841841
ID_BITMASK_PERM,
842842
ID_SWAP,
843843
ID_REVERSE,
844-
ID_BROADCAST
844+
ID_BROADCAST,
845+
ID_FFT,
846+
ID_ROTATE
845847
};
846848

849+
// clang-format off
847850
enum EncBits : unsigned {
848851

849852
// swizzle mode encodings
@@ -854,6 +857,14 @@ enum EncBits : unsigned {
854857
BITMASK_PERM_ENC = 0x0000,
855858
BITMASK_PERM_ENC_MASK = 0x8000,
856859

860+
FFT_MODE_ENC = 0xE000,
861+
862+
ROTATE_MODE_ENC = 0xC000,
863+
FFT_ROTATE_MODE_MASK = 0xF000,
864+
865+
ROTATE_MODE_LO = 0xC000,
866+
FFT_MODE_LO = 0xE000,
867+
857868
// QUAD_PERM encodings
858869

859870
LANE_MASK = 0x3,
@@ -869,8 +880,21 @@ enum EncBits : unsigned {
869880

870881
BITMASK_AND_SHIFT = 0,
871882
BITMASK_OR_SHIFT = 5,
872-
BITMASK_XOR_SHIFT = 10
883+
BITMASK_XOR_SHIFT = 10,
884+
885+
// FFT encodings
886+
887+
FFT_SWIZZLE_MASK = 0x1F,
888+
FFT_SWIZZLE_MAX = 0x1F,
889+
890+
// ROTATE encodings
891+
ROTATE_MAX_SIZE = 0x1F,
892+
ROTATE_DIR_SHIFT = 10, // bit position of rotate direction
893+
ROTATE_DIR_MASK = 0x1,
894+
ROTATE_SIZE_SHIFT = 5, // bit position of rotate size
895+
ROTATE_SIZE_MASK = ROTATE_MAX_SIZE,
873896
};
897+
// clang-format on
874898

875899
} // namespace Swizzle
876900

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -645,14 +645,18 @@ unsigned const DfmtNfmt2UFmtGFX11[] = {
645645

646646
namespace Swizzle {
647647

648+
// clang-format off
648649
// This must be in sync with llvm::AMDGPU::Swizzle::Id enum members, see SIDefines.h.
649-
const char* const IdSymbolic[] = {
650+
const char *const IdSymbolic[] = {
650651
"QUAD_PERM",
651652
"BITMASK_PERM",
652653
"SWAP",
653654
"REVERSE",
654655
"BROADCAST",
656+
"FFT",
657+
"ROTATE",
655658
};
659+
// clang-format on
656660

657661
} // namespace Swizzle
658662

‎llvm/test/MC/AMDGPU/ds_swizzle.s

Lines changed: 131 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,131 @@
1+
// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck -check-prefix=GFX7 %s
2+
// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GFX8 %s
3+
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
4+
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10PLUS %s
5+
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX10PLUS %s
6+
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck -check-prefix=GFX10PLUS %s
7+
8+
// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck -check-prefix=ERROR-PREGFX9 %s --implicit-check-not=error:
9+
// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=ERROR-PREGFX9 %s --implicit-check-not=error:
10+
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 -show-encoding %s 2>&1 | FileCheck -check-prefix=ERROR %s --implicit-check-not=error:
11+
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck -check-prefix=ERROR %s --implicit-check-not=error:
12+
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck -check-prefix=ERROR %s --implicit-check-not=error:
13+
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck -check-prefix=ERROR %s --implicit-check-not=error:
14+
15+
//==============================================================================
16+
// FFT mode
17+
18+
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0)
19+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
20+
// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
21+
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
22+
23+
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,5)
24+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
25+
// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,5) ; encoding: [0x05,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
26+
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,5) ; encoding: [0x05,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
27+
28+
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16)
29+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
30+
// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16) ; encoding: [0x10,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
31+
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16) ; encoding: [0x10,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
32+
33+
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31)
34+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
35+
// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31) ; encoding: [0x1f,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
36+
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31) ; encoding: [0x1f,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
37+
38+
ds_swizzle_b32 v5, v1 offset:0xf000
39+
// GFX7: ds_swizzle_b32 v5, v1 offset:61440 ; encoding: [0x00,0xf0,0xd4,0xd8,0x01,0x00,0x00,0x05]
40+
// GFX8: ds_swizzle_b32 v5, v1 offset:61440 ; encoding: [0x00,0xf0,0x7a,0xd8,0x01,0x00,0x00,0x05]
41+
// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xf0,0x7a,0xd8,0x01,0x00,0x00,0x05]
42+
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xf0,0xd4,0xd8,0x01,0x00,0x00,0x05]
43+
44+
45+
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,32)
46+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
47+
// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: FFT swizzle must be in the interval [0,31]
48+
49+
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,-2)
50+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
51+
// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: FFT swizzle must be in the interval [0,31]
52+
53+
ds_swizzle_b32 v5, v1 offset:swizzle(FFT)
54+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
55+
// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: expected a comma
56+
57+
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16,31)
58+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
59+
// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: expected a closing parentheses
60+
61+
//==============================================================================
62+
// ROTATE mode
63+
64+
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0)
65+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
66+
// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05]
67+
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
68+
69+
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,0)
70+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
71+
// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,0) ; encoding: [0x00,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05]
72+
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,0) ; encoding: [0x00,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
73+
74+
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1)
75+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
76+
// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1) ; encoding: [0x20,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05]
77+
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1) ; encoding: [0x20,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
78+
79+
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,1)
80+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
81+
// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,1) ; encoding: [0x20,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05]
82+
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,1) ; encoding: [0x20,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
83+
84+
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,31)
85+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
86+
// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,31) ; encoding: [0xe0,0xc3,0x7a,0xd8,0x01,0x00,0x00,0x05]
87+
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,31) ; encoding: [0xe0,0xc3,0xd4,0xd8,0x01,0x00,0x00,0x05]
88+
89+
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,31)
90+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
91+
// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,31) ; encoding: [0xe0,0xc7,0x7a,0xd8,0x01,0x00,0x00,0x05]
92+
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,31) ; encoding: [0xe0,0xc7,0xd4,0xd8,0x01,0x00,0x00,0x05]
93+
94+
ds_swizzle_b32 v5, v1 offset:0xd000
95+
// GFX7: ds_swizzle_b32 v5, v1 offset:53248 ; encoding: [0x00,0xd0,0xd4,0xd8,0x01,0x00,0x00,0x05]
96+
// GFX8: ds_swizzle_b32 v5, v1 offset:53248 ; encoding: [0x00,0xd0,0x7a,0xd8,0x01,0x00,0x00,0x05]
97+
// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xd0,0x7a,0xd8,0x01,0x00,0x00,0x05]
98+
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xd0,0xd4,0xd8,0x01,0x00,0x00,0x05]
99+
100+
101+
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,2,31)
102+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
103+
// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: direction must be 0 (left) or 1 (right)
104+
105+
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,-1,31)
106+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
107+
// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: direction must be 0 (left) or 1 (right)
108+
109+
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,32)
110+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
111+
// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: number of threads to rotate must be in the interval [0,31]
112+
113+
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,-2)
114+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
115+
// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: number of threads to rotate must be in the interval [0,31]
116+
117+
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE)
118+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
119+
// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: expected a comma
120+
121+
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0)
122+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
123+
// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: expected a comma
124+
125+
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1)
126+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
127+
// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: expected a comma
128+
129+
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1,2)
130+
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
131+
// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: expected a closing parentheses

‎llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8257,15 +8257,15 @@ ds_read_u16 a5, v1
82578257
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
82588258
ds_read_u16 a5, v1 offset:4
82598259

8260-
// GFX90A: ds_swizzle_b32 a5, v1 offset:65535 ; encoding: [0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0x05]
8260+
// GFX90A: ds_swizzle_b32 a5, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0x05]
82618261
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
82628262
ds_swizzle_b32 a5, v1 offset:65535
82638263

8264-
// GFX90A: ds_swizzle_b32 a255, v1 offset:65535 ; encoding: [0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0xff]
8264+
// GFX90A: ds_swizzle_b32 a255, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0xff]
82658265
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
82668266
ds_swizzle_b32 a255, v1 offset:65535
82678267

8268-
// GFX90A: ds_swizzle_b32 a5, v255 offset:65535 ; encoding: [0xff,0xff,0x7a,0xda,0xff,0x00,0x00,0x05]
8268+
// GFX90A: ds_swizzle_b32 a5, v255 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0x7a,0xda,0xff,0x00,0x00,0x05]
82698269
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
82708270
ds_swizzle_b32 a5, v255 offset:65535
82718271

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