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fix the comments
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6 files changed

+12
-12
lines changed

6 files changed

+12
-12
lines changed

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17934,8 +17934,8 @@ AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
1793417934
if (!ShiftLHS->hasOneUse())
1793517935
return false;
1793617936

17937-
if ((ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
17938-
!ShiftLHS.getOperand(0)->hasOneUse()))
17937+
if (ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
17938+
!ShiftLHS.getOperand(0)->hasOneUse())
1793917939
return false;
1794017940

1794117941
// If ShiftLHS is unsigned bit extraction: ((x >> C) & mask), then do not

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1077,8 +1077,8 @@ bool AMDGPUTargetLowering::isDesirableToCommuteWithShift(
10771077
if (!ShiftLHS->hasOneUse())
10781078
return false;
10791079

1080-
if ((ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
1081-
!ShiftLHS.getOperand(0)->hasOneUse()))
1080+
if (ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
1081+
!ShiftLHS.getOperand(0)->hasOneUse())
10821082
return false;
10831083

10841084
// Always commute pre-type legalization and right shifts.

llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13884,8 +13884,8 @@ ARMTargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
1388413884
if (!ShiftLHS->hasOneUse())
1388513885
return false;
1388613886

13887-
if ((ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
13888-
!ShiftLHS.getOperand(0)->hasOneUse()))
13887+
if (ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
13888+
!ShiftLHS.getOperand(0)->hasOneUse())
1388913889
return false;
1389013890

1389113891
if (Level == BeforeLegalizeTypes)

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2163,8 +2163,8 @@ bool HexagonTargetLowering::isDesirableToCommuteWithShift(
21632163
if (!ShiftLHS->hasOneUse())
21642164
return false;
21652165

2166-
if ((ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
2167-
!ShiftLHS.getOperand(0)->hasOneUse()))
2166+
if (ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
2167+
!ShiftLHS.getOperand(0)->hasOneUse())
21682168
return false;
21692169

21702170
return true;

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19177,8 +19177,8 @@ bool PPCTargetLowering::isDesirableToCommuteWithShift(
1917719177
if (!ShiftLHS->hasOneUse())
1917819178
return false;
1917919179

19180-
if ((ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
19181-
!ShiftLHS.getOperand(0)->hasOneUse()))
19180+
if (ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
19181+
!ShiftLHS.getOperand(0)->hasOneUse())
1918219182
return false;
1918319183

1918419184
return true;

llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -60684,8 +60684,8 @@ bool X86TargetLowering::isDesirableToCommuteWithShift(
6068460684
if (!ShiftLHS->hasOneUse())
6068560685
return false;
6068660686

60687-
if ((ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
60688-
!ShiftLHS.getOperand(0)->hasOneUse()))
60687+
if (ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
60688+
!ShiftLHS.getOperand(0)->hasOneUse())
6068960689
return false;
6069060690

6069160691
return true;

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