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davemgreendavemgreen
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[AArch64] Add mayStore to more store instructions
As in #121565 we need to mark all stores as mayStore, hasSideEffects is not enough to prevent moving loads past the instructions. And marking the instructions as mayStore is a sensible thing to do on its own.
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+25
-18
lines changed

5 files changed

+25
-18
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5028,6 +5028,7 @@ class BaseStoreUnprivilegedLSUI<bits<2> sz, dag oops, dag iops, string asm>
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let Inst{9-5} = Rn;
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let Inst{4-0} = Rt;
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let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
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let mayStore = 1;
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}
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multiclass StoreUnprivilegedLSUI<bits<2> sz, RegisterClass regtype, string asm> {
@@ -12532,6 +12533,7 @@ class Store64BV<bits<3> opc, string asm_inst, list<dag> pat = []>
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(ins GPR64x8:$Rt, GPR64sp:$Rn), (outs GPR64:$Rs), pat> {
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bits<5> Rs;
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let Inst{20-16} = Rs;
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let mayStore = 1;
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}
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class MOPSMemoryCopyMoveBase<bit isMove, bits<2> opcode, bits<2> op1,

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2799,14 +2799,17 @@ def : Pat<(int_aarch64_ldg GPR64:$Rt, (am_indexeds9s128 GPR64sp:$Rn, simm9s16:$
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def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>;
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let mayLoad = 1 in
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def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]",
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(outs GPR64:$Rt), (ins GPR64sp:$Rn)>;
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let mayStore = 1 in {
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def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]",
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(outs), (ins GPR64:$Rt, GPR64sp:$Rn)>;
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def STZGM : MemTagVector<0, "stzgm", "\t$Rt, [$Rn]",
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(outs), (ins GPR64:$Rt, GPR64sp:$Rn)> {
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let Inst{23} = 0;
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}
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} // mayStore = 1
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defm STG : MemTagStore<0b00, "stg">;
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defm STZG : MemTagStore<0b01, "stzg">;
@@ -10018,8 +10021,10 @@ foreach i = 0-7 in {
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}
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let Predicates = [HasLS64] in {
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let mayLoad = 1 in
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def LD64B: LoadStore64B<0b101, "ld64b", (ins GPR64sp:$Rn),
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(outs GPR64x8:$Rt)>;
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let mayStore = 1 in
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def ST64B: LoadStore64B<0b001, "st64b", (ins GPR64x8:$Rt, GPR64sp:$Rn),
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(outs)>;
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def ST64BV: Store64BV<0b011, "st64bv">;

‎llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/mte-instructions.s

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -215,12 +215,12 @@ stzgm xzr, [x2]
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# CHECK-NEXT: 2 4 0.50 * U ldgm x0, [x1]
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# CHECK-NEXT: 2 4 0.50 * U ldgm x1, [sp]
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# CHECK-NEXT: 2 4 0.50 * U ldgm xzr, [x2]
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# CHECK-NEXT: 1 1 0.50 U stgm x0, [x1]
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# CHECK-NEXT: 1 1 0.50 U stgm x1, [sp]
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# CHECK-NEXT: 1 1 0.50 U stgm xzr, [x2]
221-
# CHECK-NEXT: 1 1 0.50 U stzgm x0, [x1]
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# CHECK-NEXT: 1 1 0.50 U stzgm x1, [sp]
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# CHECK-NEXT: 1 1 0.50 U stzgm xzr, [x2]
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# CHECK-NEXT: 1 1 0.50 * U stgm x0, [x1]
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# CHECK-NEXT: 1 1 0.50 * U stgm x1, [sp]
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# CHECK-NEXT: 1 1 0.50 * U stgm xzr, [x2]
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# CHECK-NEXT: 1 1 0.50 * U stzgm x0, [x1]
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# CHECK-NEXT: 1 1 0.50 * U stzgm x1, [sp]
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# CHECK-NEXT: 1 1 0.50 * U stzgm xzr, [x2]
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# CHECK: Resources:
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# CHECK-NEXT: [0.0] - Ampere1BUnitA

‎llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-mte-instructions.s

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -215,12 +215,12 @@ stzgm xzr, [x2]
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# CHECK-NEXT: 1 4 0.33 * U ldgm x0, [x1]
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# CHECK-NEXT: 1 4 0.33 * U ldgm x1, [sp]
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# CHECK-NEXT: 1 4 0.33 * U ldgm xzr, [x2]
218-
# CHECK-NEXT: 2 1 0.50 U stgm x0, [x1]
219-
# CHECK-NEXT: 2 1 0.50 U stgm x1, [sp]
220-
# CHECK-NEXT: 2 1 0.50 U stgm xzr, [x2]
221-
# CHECK-NEXT: 2 1 0.50 U stzgm x0, [x1]
222-
# CHECK-NEXT: 2 1 0.50 U stzgm x1, [sp]
223-
# CHECK-NEXT: 2 1 0.50 U stzgm xzr, [x2]
218+
# CHECK-NEXT: 2 1 0.50 * U stgm x0, [x1]
219+
# CHECK-NEXT: 2 1 0.50 * U stgm x1, [sp]
220+
# CHECK-NEXT: 2 1 0.50 * U stgm xzr, [x2]
221+
# CHECK-NEXT: 2 1 0.50 * U stzgm x0, [x1]
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# CHECK-NEXT: 2 1 0.50 * U stzgm x1, [sp]
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# CHECK-NEXT: 2 1 0.50 * U stzgm xzr, [x2]
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225225
# CHECK: Resources:
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# CHECK-NEXT: [0.0] - N2UnitB

‎llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-mte-instructions.s

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -215,12 +215,12 @@ stzgm xzr, [x2]
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# CHECK-NEXT: 1 4 0.33 * U ldgm x0, [x1]
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# CHECK-NEXT: 1 4 0.33 * U ldgm x1, [sp]
217217
# CHECK-NEXT: 1 4 0.33 * U ldgm xzr, [x2]
218-
# CHECK-NEXT: 2 1 0.50 U stgm x0, [x1]
219-
# CHECK-NEXT: 2 1 0.50 U stgm x1, [sp]
220-
# CHECK-NEXT: 2 1 0.50 U stgm xzr, [x2]
221-
# CHECK-NEXT: 2 1 0.50 U stzgm x0, [x1]
222-
# CHECK-NEXT: 2 1 0.50 U stzgm x1, [sp]
223-
# CHECK-NEXT: 2 1 0.50 U stzgm xzr, [x2]
218+
# CHECK-NEXT: 2 1 0.50 * U stgm x0, [x1]
219+
# CHECK-NEXT: 2 1 0.50 * U stgm x1, [sp]
220+
# CHECK-NEXT: 2 1 0.50 * U stgm xzr, [x2]
221+
# CHECK-NEXT: 2 1 0.50 * U stzgm x0, [x1]
222+
# CHECK-NEXT: 2 1 0.50 * U stzgm x1, [sp]
223+
# CHECK-NEXT: 2 1 0.50 * U stzgm xzr, [x2]
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225225
# CHECK: Resources:
226226
# CHECK-NEXT: [0.0] - N3UnitB

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