@@ -999,7 +999,9 @@ class AArch64BtiPac final : public AArch64 {
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private:
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bool btiHeader; // bti instruction needed in PLT Header and Entry
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- bool pacEntry; // autia1716 instruction needed in PLT Entry
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+ bool pacEntry; // Authenticated branch needed in PLT Entry
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+ bool pacUseHint =
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+ true ; // Use hint space instructions for authenticated branch in PLT entry
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};
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} // namespace
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@@ -1016,6 +1018,10 @@ AArch64BtiPac::AArch64BtiPac(Ctx &ctx) : AArch64(ctx) {
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// from properties in the objects, so we use the command line flag.
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pacEntry = ctx.arg .zPacPlt ;
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+ if (llvm::any_of (ctx.aarch64PauthAbiCoreInfo ,
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+ [](uint8_t c) { return c != 0 ; }))
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+ pacUseHint = false ;
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+
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if (btiHeader || pacEntry) {
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pltEntrySize = 24 ;
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ipltEntrySize = 24 ;
@@ -1066,9 +1072,13 @@ void AArch64BtiPac::writePlt(uint8_t *buf, const Symbol &sym,
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0x11 , 0x02 , 0x40 , 0xf9 , // ldr x17, [x16, Offset(&(.got.plt[n]))]
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0x10 , 0x02 , 0x00 , 0x91 // add x16, x16, Offset(&(.got.plt[n]))
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};
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+ const uint8_t pacHintBr[] = {
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+ 0x9f , 0x21 , 0x03 , 0xd5 , // autia1716
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+ 0x20 , 0x02 , 0x1f , 0xd6 // br x17
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+ };
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const uint8_t pacBr[] = {
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- 0x9f , 0x21 , 0x03 , 0xd5 , // autia1716
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- 0x20 , 0x02 , 0x1f , 0xd6 // br x17
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+ 0x30 , 0x0a , 0x1f , 0xd7 , // braa x17, x16
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+ 0x1f , 0x20 , 0x03 , 0xd5 // nop
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};
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const uint8_t stdBr[] = {
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0x20 , 0x02 , 0x1f , 0xd6 , // br x17
@@ -1097,7 +1107,8 @@ void AArch64BtiPac::writePlt(uint8_t *buf, const Symbol &sym,
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relocateNoSym (buf + 8 , R_AARCH64_ADD_ABS_LO12_NC, gotPltEntryAddr);
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if (pacEntry)
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- memcpy (buf + sizeof (addrInst), pacBr, sizeof (pacBr));
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+ memcpy (buf + sizeof (addrInst), (pacUseHint ? pacHintBr : pacBr),
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+ sizeof (pacUseHint ? pacHintBr : pacBr));
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else
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memcpy (buf + sizeof (addrInst), stdBr, sizeof (stdBr));
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if (!hasBti)
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